Test Executable ASIC for Semiconductor Memory Testing
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Solution Overview
Problem
The existing test systems for semiconductor memory devices are costly and time-consuming, particularly due to the need for expensive general-purpose testers and extensive wiring for firmware communication, which limits the efficiency and scalability of functional tests.
Innovation Solution
A test system that includes a first test board with a test executable integrated circuit (ASIC) and a first measuring apparatus, where firmware is stored in the device under test (DUT) in advance, allowing the ASIC to execute tests independently and report results, reducing the need for dedicated wiring and expensive testers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If general-purpose testers are used for functional testing of semiconductor memory devices, then comprehensive test capabilities are achieved, but test costs and time increase significantly
Solution Approach 1:
The test system is segmented into two parts: a simple first tester that provides basic test signals and a test executable integrated circuit (ASIC) mounted on the test board that contains the complex test logic and firmware. This segmentation allows the expensive general-purpose tester functions to be replaced with a dedicated, simplified tester combined with an application-specific test chip, reducing test time and cost while maintaining comprehensive test capabilities.
Solution Approach 2:
A test executable integrated circuit (ASIC) is introduced as an intermediary between the simple first tester and the device under test. The ASIC contains firmware that executes comprehensive test sequences, acting as a mediator that enables complex testing functionality without requiring an expensive general-purpose tester, thus reducing test time and costs.
2Measurement precision
If firmware is communicated through dedicated wiring between tester and DUT, then test control precision is improved, but device complexity and cost increase
Solution Approach 1:
The test executable integrated circuit (ASIC) is designed to be universal and reconfigurable through firmware loading. Instead of dedicated wiring for each test function, the ASIC can be programmed with different firmware to perform various test sequences and control functions. This multi-functionality reduces wiring complexity while maintaining precise test control through software-based configuration.
Solution Approach 2:
The patent replaces the mechanical/physical wiring system for firmware communication with an electronic software-based system. Firmware is transmitted and executed electronically within the ASIC, substituting complex physical wiring connections with software-controlled logic, thereby reducing wiring complexity while maintaining precise test control.
3Productivity
If multiple DUTs are tested in parallel, then productivity increases, but test system complexity and coordination difficulty increase
Solution Approach 1:
Multiple test executable integrated circuits (ASICs) are merged onto a single test board, each capable of independently testing a device under test. The first tester provides coordinated control signals to multiple ASICs simultaneously, enabling parallel testing of multiple DUTs. This merging approach increases productivity while the standardized ASIC design keeps system coordination complexity manageable.
Data Source
AI summary
According to a certain embodiment, the test system includes a first test board, a test executable integrated circuit, and a first measuring apparatus. A device under test (DUT) is mounted on the first test board. The test executable integrated circuit is mounted on the first test board, and is configured to read firmware stored in the DUT in advance and to test the DUT. The first measuring apparatus instructs the test executable integrated circuit to start a test of the DUT. There are provided the test system, the test method, and the non-transitory computer readable medium, capable of reducing costs required for tests and also of shortening test time.