Test Fixture Short Branch Routing for DRAM Signal Integrity

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Solution Overview

Problem

Existing test fixtures for high-frequency signal testing of packaged DRAM chips suffer from significant signal attenuation due to signal reflection, which is exacerbated by long branch routing lengths causing phase differences and signal superposition, leading to reduced amplitude and inefficient testing.

Innovation Solution

A test fixture with a signal test board featuring short branch routings connecting test points to circuit routings, minimizing phase differences and signal attenuation, ensuring minimal reduction in high-frequency signal amplitude and enabling accurate testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If long branch routing is used to connect test point to circuit routing, then the test fixture can accommodate standard layouts, but signal attenuation increases due to phase differences and signal superposition

Engineering Contradiction:
Improvelayout accommodationVSAvoidsignal attenuation
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent extracts the harmful effect of long branch routing by removing the unnecessary routing length. The test point is repositioned to directly overlap with the circuit routing, eliminating the branch routing entirely or reducing it to minimal length, thus extracting the source of signal attenuation while maintaining manufacturing compatibility

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar routing approach to a vertical stacking approach by placing the test point in the same physical location as the circuit routing but on a different layer. This dimensional change eliminates the need for long horizontal branch routing while maintaining electrical connectivity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If short branch routing is used to minimize signal attenuation, then high-frequency signal integrity is maintained, but the design flexibility and layout accommodation are reduced

Engineering Contradiction:
Improvesignal attenuationVSAvoidlayout flexibility
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

By utilizing vertical layer stacking, the patent achieves short branch routing (minimal horizontal distance) while maintaining layout flexibility. The test point can be positioned vertically above or below the circuit routing on adjacent layers, preserving design adaptability without compromising signal integrity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests the test point structure within the circuit routing structure by positioning them at the same lateral coordinates but on different layers. This nesting approach minimizes the branch routing footprint while maintaining both signal quality and design flexibility for various circuit layouts

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11933815B2Test fixture
Publication Date: 2024.03.19 CHANGXIN MEMORY TECH INC
  • US11933815B2 patent drawing
  • US11933815B2 patent drawing
  • US11933815B2 patent drawing

AI summary

A test fixture includes a signal test board, a circuit routing, and a branch routing. The signal test board includes a first surface and a second surface. The first surface has a first pin and a test point. The second surface has a second pin. The circuit routing is located in the signal test board and configured to connect the first pin and a corresponding second pin. A portion of the circuit routing includes an upper routing connected with one first pin, a lower routing connected with one second pin, and a via-hole routing connected with two ends of the upper routing and the lower routing. One end, connected with the via-hole routing, of the upper routing is located in a projection area of the corresponding test point. The branch routing is located in the signal test board and configured to connect the test point with a corresponding upper routing.