Test Generation Using Marker Statements for Hardware Mode Synchronization
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Solution Overview
Problem
In hardware testing, especially during post-silicon validation, achieving synchronization among verification environment components with respect to the state of the Design Under Test (DUT) is challenging when the expected full state is unavailable, leading to lower quality test cases and resource-intensive state-aware test generation.
Innovation Solution
The use of predetermined marker statements to designate mode changes in a test case, allowing for pseudo-state aware test generation that modifies the DUT's mode of operation, enabling test instruction generation and execution without requiring a full state model, thus maintaining simplicity and light weight.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If state-aware test generation is used to achieve mode synchronization, then test quality improves, but resource requirements and system complexity increase
Solution Approach 1:
The patent segments the state information into discrete mode indicators that can be independently tracked and synchronized. Instead of managing the entire system state, the verification environment components track only the relevant mode state, reducing complexity while maintaining test quality.
Solution Approach 2:
The patent introduces marker statements as intermediary elements that facilitate mode synchronization. These markers act as communication signals between test generation components and verification components, enabling coordination without requiring complex state-sharing mechanisms.
2Measurement precision
If full state model is used for test generation, then mode synchronization accuracy improves, but resource consumption increases
Solution Approach 1:
The patent extracts only the essential mode information from the full system state, discarding unnecessary details. By taking out only the relevant mode indicators needed for synchronization, the system achieves accurate mode tracking with minimal resource consumption.
Solution Approach 2:
The patent applies partial action by implementing pseudo-state awareness that provides sufficient mode synchronization information without the overhead of complete state awareness. This partial approach delivers the necessary precision for mode synchronization while consuming fewer resources than full state tracking.
3Ease of manufacture
If pseudo-state aware test generation is used, then framework simplicity is maintained, but test case quality may decrease
Solution Approach 1:
The patent changes the parameter representation from full state information to mode indicator parameters. This parameter transformation maintains framework simplicity by working with lighter-weight data structures while improving test quality through better mode synchronization capabilities.
Data Source
AI summary
A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.