Test-Key Circuit Structure Matrix Transistor Testing
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Solution Overview
Problem
Conventional test methods for test-keys are limited by slow measuring speed due to testing devices one at a time, especially when the number of devices under test is large.
Innovation Solution
A circuit structure and test method utilizing a matrix arrangement of transistors with conductive contact pads, where transistors are turned on row-by-row with non-overlapping driving pulses, allowing for simultaneous testing of multiple devices without the need for coding and decoding, and incorporating a scan-pulse generating circuit to automate the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional test method tests one device at every turn, then the test process is simple to implement, but the measuring speed is slow when the amount of devices is large
Solution Approach 1:
The patent segments the array of devices under test into multiple rows, with each row controllable by a separate gate electrode. This allows independent control and testing of different rows, enabling parallel testing operations while maintaining a systematic circuit structure.
Solution Approach 2:
The patent merges multiple source electrodes and drain electrodes into shared conductive contact pads that serve multiple transistors simultaneously. This reduces the total number of required contact pads and enables parallel testing of multiple devices without proportionally increasing circuit complexity.
2Quantity of substance
If the amount of devices under test is large, then the testing coverage is comprehensive, but the test time increases due to sequential testing
Solution Approach 1:
The patent employs periodic scanning signals applied to gate electrodes to systematically activate different rows of devices at different time intervals. This periodic activation pattern enables comprehensive testing of all devices while organizing the test sequence efficiently to minimize total test time.
Solution Approach 2:
The patent prepares the test circuit structure in advance with all devices connected to shared contact pads and organized in rows with common gate control. This preliminary arrangement allows immediate parallel testing to begin without sequential connection setup, reducing overall test time for large device arrays.
3Productivity
If multiple devices are tested simultaneously, then the test speed increases, but the circuit structure becomes more complex
Solution Approach 1:
The patent designs conductive contact pads that serve multiple functions: they act as common source connections for multiple transistors, common drain connections for other transistors, and interface points for test signal application. This multi-functionality reduces the number of dedicated connections needed while enabling parallel testing of multiple devices.
Solution Approach 2:
The patent transitions from one-dimensional sequential testing to two-dimensional parallel testing by organizing devices in rows and columns with independent gate control. This dimensional change allows simultaneous testing across multiple rows while maintaining organized circuit structure through systematic electrode arrangement.
Data Source
AI summary
A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.