Test Key Layout for Monitoring Semiconductor Pattern Misalignments
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Solution Overview
Problem
Conventional litho-litho-etch (LLE) processes face challenges in achieving precise alignment of patterns, leading to misalignment issues that affect the electrical performance of semiconductor products, necessitating a method to correct and monitor pattern shifts.
Innovation Solution
A test key layout with multiple test keys, each comprising an operating voltage line, grounding voltage lines, and testing electrodes, where the position and length of the electrodes are sequentially shifted or changed to measure misalignment offsets by determining resistance variations across the keys, allowing for precise measurement of pattern misalignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If LLE process is used to manufacture pattern features with resolution beyond conventional lithographic limitations, then feature size resolution is improved, but alignment precision between exposure steps deteriorates
Solution Approach 1:
The patent applies preliminary action by forming test keys with testing electrodes at multiple predetermined positions before the main production process. These test keys serve as reference structures that pre-establish measurement points for detecting alignment offsets between first and second exposure patterns, enabling precise measurement without affecting the main feature fabrication.
Solution Approach 2:
The patent uses test keys as intermediary structures that mediate between the exposure process and measurement process. The testing electrodes within test keys act as intermediate reference elements that translate complex alignment issues into measurable resistance variations, facilitating precise alignment detection without directly interfering with the main pattern formation.
2Productivity
If alignment correction is implemented in LLE process, then product yield is improved, but process complexity increases
Solution Approach 1:
The patent applies self-service by enabling the test keys to automatically indicate alignment status through their electrical resistance characteristics. The testing electrodes inherently provide measurement functionality through their geometric relationship with voltage lines, eliminating the need for separate complex measurement apparatus and allowing alignment detection to be self-contained within the test key structure itself.
Solution Approach 2:
The patent replaces complex mechanical alignment measurement systems with electrical resistance measurement. Instead of using mechanical gauges or optical interferometry to detect alignment offsets, the invention uses simple electrical resistance measurements of test keys, which can be performed using standard semiconductor testing equipment, thereby reducing process complexity.
3Measurement precision
If multiple test keys with sequentially shifted electrodes are used, then measurement precision of misalignment offset is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the measurement function into multiple discrete test keys, each with testing electrodes at specific predetermined positions. This segmentation allows the misalignment offset to be measured at multiple points, and the overall alignment accuracy is improved by combining measurements from all test keys. Each test key is a simple structure, but collectively they provide high-precision measurement capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate monitoring and correction of pattern misalignments, improving product yield by providing a method to derive subtle offset measurements, critical for advanced semiconductor manufacturing, especially at technology nodes below 28 nm.
Implementation Method 1
measuring the resistance of each test key and determine the misalignment offset of layout pattern from first exposure process and layout pattern from second exposure process
Data Source
AI summary
A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (Vdd) line and a grounding voltage (Vss) line, wherein the patterns of test keys are defined by an overlapped portion of a first exposure pattern and a second exposure pattern, and the position of testing electrode is shifted sequentially in one direction in order of the test keys.