Test Key Structure for Via Resistance Measurement
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Solution Overview
Problem
Current semiconductor processes face challenges in precisely measuring the resistance of vias during wafer acceptance tests, which is crucial for ensuring the stability and quality of semiconductor elements, as existing testkey structures lack the capability to accurately simulate and measure the resistance of target via arrays.
Innovation Solution
A novel testkey structure with a substrate and overlapping conductive lines and vias, allowing for precise measurement of via resistance using the Kelvin (4-wire) resistance method, where the resistance of each via is calculated using the measured voltage and current values, enabling simulation of various via arrangements to match the target via array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testkey structures are used, then the test structure is simple, but the measurement precision of via resistance is insufficient
Solution Approach 1:
The testkey structure is segmented into multiple functional components: first conductive lines for current injection, second conductive lines for voltage sensing, and via arrays arranged in specific patterns. This segmentation allows separate optimization of current path and voltage measurement path, enabling precise via resistance measurement while maintaining structural organization
Solution Approach 2:
The patent introduces dummy vias as intermediary elements between the actual via array and the conductive lines. These dummy vias serve as mediators to extend the conductive paths and improve measurement accuracy by eliminating edge effects and contact resistance influences, thereby enhancing measurement precision without directly modifying the target via array
2Adaptability or versatility
If existing testkey structures are used, then the device complexity is low, but the ability to simulate complex via arrays is limited
Solution Approach 1:
The testkey structure is designed with universal applicability through configurable via arrays that can simulate different via patterns (e.g., 1x1, 2x2, 3x3 arrangements). The conductive lines and via arrays are arranged to accommodate multiple measurement scenarios, allowing a single testkey structure to serve multiple via array simulation purposes, thereby enhancing adaptability without proportionally increasing complexity
Solution Approach 2:
The patent transitions from simple linear conductive paths to two-dimensional overlapping conductive line arrangements with via arrays positioned at intersection regions. This dimensional expansion allows simulation of complex via arrays by creating multiple measurement regions within the same testkey structure, significantly improving via array simulation capability through spatial arrangement rather than increasing component count
3Measurement precision
If conventional measurement methods are used, then the process is simple, but the measurement precision of via resistance is insufficient
Solution Approach 1:
The testkey structure employs asymmetric conductive line arrangements where first conductive lines and second conductive lines have different functions and configurations. The current injection paths and voltage sensing paths are deliberately made asymmetric to eliminate measurement errors from contact resistance and lead resistance, thereby improving via resistance measurement precision while managing measurement complexity through functional differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise measurement and simulation of via resistance, aiding in the adjustment of input/output voltage for integrated circuits and monitoring of the via manufacturing process, thereby enhancing the accuracy of semiconductor process evaluation and yield.
Implementation Method 1
a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines
Implementation Method 2
allowing for precise measurement of via resistance using the Kelvin (4-wire) resistance method
Data Source
AI summary
The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure.