Test Mode Circuit Reducing Semiconductor Testing Pads

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Solution Overview

Problem

Current semiconductor device testing methods require multiple pads to be connected to a test apparatus, which increases the complexity and cost of testing multiple devices simultaneously.

Innovation Solution

A test mode circuit that includes a test mode activating signal generation unit, a test clock generation unit, a test control signal generation unit, and an internal control signal generation unit, allowing for a reduced number of pads to be connected while performing a test operation by generating necessary signals and control signals from input data and control clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple pads are connected to test apparatus for testing semiconductor devices, then testing capability is improved, but device complexity and testing cost increase

Engineering Contradiction:

Improvetesting capabilityVSAvoidtesting complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The test mode circuit enables existing pads to serve dual purposes: normal operational pads and test pads. By generating test mode activating signals, test clocks, and test control signals through the existing pad structure, the circuit allows a reduced number of pads to perform both operational and testing functions, eliminating the need for separate dedicated test pads for each device

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the test signal input function with the existing pad structure by having the test mode activating signal generation unit receive test signals through pads that are already connected for operational purposes. This consolidation allows multiple semiconductor devices to be tested simultaneously through shared pad connections, reducing overall testing complexity

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If multiple pads are connected to test apparatus for testing semiconductor devices, then testing capability is improved, but testing cost increases

Engineering Contradiction:

Improvetesting capabilityVSAvoidtesting cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The test mode circuit generates its own control signals internally rather than requiring external test apparatus to provide all test signals. The test clock generation unit and test control signal generation unit create necessary timing and control signals from the input test signal, reducing the complexity and cost of external testing equipment

Inventive Principle:

Principle #25Self-service

3Productivity

If reduced number of pads are used for testing, then testing efficiency is improved, but signal generation capability must be enhanced

Engineering Contradiction:

Improvetesting efficiencyVSAvoidsignal generation capability

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The test mode circuit is divided into distinct functional units that each handle specific signal generation tasks: test mode activating signal generation unit, test clock generation unit, test control signal generation unit, and internal control signal generation unit. This segmentation allows the complex signal generation capability to be distributed across modular components, making the enhanced functionality manageable and implementable

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The test mode activating signal generation unit prepares the system for testing by generating activation signals that trigger the subsequent signal generation units. The test clock generation unit pre-generates timing signals, and the test control signal generation unit prepares control signals before actual testing begins, ensuring that all necessary signals are ready when testing starts, thus improving testing efficiency

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9817065B2Test mode circuit and semiconductor device including the same

Publication Date: 2017.11.14 SK HYNIX INC

AI summary

A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.