Test Mode Circuit Selective Reset Logic
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Solution Overview
Problem
Existing semiconductor testing methods require unconditional resetting of all test modes within a group to perform individual reset operations, leading to inefficiencies and increased time consumption, especially as the number of test modes increases.
Innovation Solution
A semiconductor device with a test mode circuit that includes multiple test group operation units, each reset and activated by specific test entry codes and global reset signals, allowing for selective and independent operation of test modes without requiring a global reset for individual operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If test modes are grouped and reset using a global reset signal, then the number of control signals is reduced and control is simplified, but all test modes in the group must be reset even when only some need resetting, leading to increased test operation time
Solution Approach 1:
The patent divides the test mode reset function into two independent segments: a global reset signal that can reset all test modes, and individual reset signals that can reset specific test modes. This segmentation allows the system to choose the appropriate reset scope (global or individual) based on the testing requirements, thereby reducing unnecessary reset operations and test operation time while maintaining control signal simplification benefits
2Loss of time
If individual test modes are reset separately, then only the needed test modes are reset, but the number of control signals increases and control becomes more complex
Solution Approach 1:
The patent implements a universal reset control mechanism where a single reset control unit can generate both global reset signals and individual reset signals based on the same control logic. This multi-functional approach allows the system to handle both global and individual reset operations through a unified control structure, reducing the overall complexity of control signals while enabling selective reset of individual test modes when needed
Data Source
AI summary
A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.