Test Mode Control Circuit for Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face issues with unintentional entry into a test mode due to signal noise or user mistakes during normal operation, leading to potential boot failures and parallel bit operation errors.
Innovation Solution
A test mode control circuit that includes a latch, a real entry signal detector, an entry signal determinator, and a mode control signal generator, which ensures that entry into the test mode is blocked during normal use by verifying the authenticity of the test command through a real entry signal, preventing accidental mode changes without requiring additional pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the test mode entering condition is made simple to satisfy, then the test mode can be easily entered, but unintentional entry into test mode occurs due to signal noise or user mistakes
Solution Approach 1:
The patent applies preliminary action by requiring a specific sequence of commands: first issuing a mode register set command to load test mode parameters, then issuing a test command. This sequential preparation ensures that only intentional test mode entries are executed, preventing unintentional entry from simple noise or mistakes while maintaining ease of legitimate test mode access.
Solution Approach 2:
The patent introduces an intermediary mechanism using the mode register as a mediator between the test command and the actual test mode execution. The mode register stores test mode parameters and acts as a verification step, ensuring that the test command is intentionally issued after proper setup, thus preventing unintentional entry while preserving operational ease for legitimate tests.
2Reliability
If additional verification mechanisms are added to prevent unintentional test mode entry, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies universality by making the mode register serve multiple functions: it stores test mode parameters, verifies the intent to enter test mode, and controls the test mode execution. This multi-functionality prevents unintentional entry without requiring separate dedicated verification circuits, thereby maintaining reliability while minimizing additional device complexity.
Solution Approach 2:
The patent implements self-service by using the existing mode register and command structure to perform the verification function. The mode register itself participates in the verification process through its contents and state, eliminating the need for external verification circuits and reducing overall device complexity while maintaining reliable unintentional entry blocking.
3Reliability
If the test mode entry condition requires a specific sequence of commands, then unintentional entry is prevented, but the test mode entering process becomes more complex
Solution Approach 1:
The patent applies preliminary action by establishing a clear preparatory sequence where the mode register set command is issued first to load test mode parameters, followed by the test command. This structured preparation makes the entry process more reliable by ensuring intentional execution, while the sequential nature of the commands actually simplifies the operation by providing a clear, step-by-step procedure rather than complex conditional logic.
Data Source
AI summary
A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.