Test Mode Signal Generating Device for Semiconductor Reliability Testing

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Solution Overview

Problem

Conventional test mode signal generating devices for semiconductor apparatuses are limited in generating a large number of test mode signals due to the restricted number of address signals, making it difficult to perform extensive reliability testing.

Innovation Solution

The proposed test mode signal generating device employs a configuration with first and second test mode signal generating units and mode conversion signals, allowing conversion between test modes using a limited number of address signals, thereby enabling the generation of an unlimited number of test mode signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a limited number of address signals are used to generate test mode signals, then the device complexity is reduced, but the number of test modes that can be generated is limited

Engineering Contradiction:
Improvenumber of test modesVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic mode conversion where the test mode signal generating unit can switch between different test modes (first test mode and second test mode) based on mode conversion signals. This dynamic switching capability allows the system to generate more test modes than the static address signal combinations would normally permit, resolving the contradiction between limited address signals and the need for extensive test coverage.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent adds a temporal dimension to test mode generation by introducing mode conversion signals that enable transitions between different test modes. Instead of relying solely on the spatial dimension of address signal combinations, the system uses time-based mode conversion to expand the effective number of test modes, thereby increasing adaptability without proportionally increasing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If more test mode signals are generated to enhance reliability testing, then the reliability testing capability is improved, but the device complexity increases

Engineering Contradiction:
Improvereliability testing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test mode signal generating unit is designed to perform multiple functions: generating test mode signals in the first test mode, generating test mode signals in the second test mode, and responding to mode conversion signals to switch between modes. This multi-functionality allows the same hardware unit to provide extensive reliability testing capability without requiring separate dedicated circuits for each test mode, thereby improving reliability testing capability while controlling device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If conventional test mode signal generating devices are used, then the device complexity is kept simple, but the number of test modes is limited to approximately half of what is needed for extensive reliability testing

Engineering Contradiction:
Improvenumber of test modesVSAvoidease of operation
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent introduces mode conversion signals as intermediaries between the address signals and the test mode signal generating unit. These mode conversion signals mediate the transition between different test modes, allowing the system to expand its test mode capability while maintaining a relatively simple address signal interface. The mode conversion signals act as a buffer layer that enables complex functionality without directly increasing the complexity of the basic address signal generation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8248096B2Test mode signal generating device
Publication Date: 2012.08.21 SK HYNIX INC
  • US8248096B2 patent drawing
  • US8248096B2 patent drawing
  • US8248096B2 patent drawing

AI summary

Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.