Test Mode Signal Generation Circuit Segmentation
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Solution Overview
Problem
Conventional test mode signal generation methods for semiconductor memory apparatuses require a large number of global lines, leading to increased wiring complexity and reduced layout margin, as they are limited by the number of address signals and cannot generate sufficient test mode signals to effectively check increasing failures during the fabrication process.
Innovation Solution
A test mode signal generation circuit comprising a pre-decoder block and a signal generation block that decodes address signals to produce exponentially increasing numbers of test mode signals through control signals, allowing for multiple test mode group signals to be generated, thereby reducing the need for extensive global lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional test mode signal generation method is used, then the number of global lines is limited by the number of address signals, but the number of test mode signals is insufficient to check increasing failures
Solution Approach 1:
The test mode signal generation is divided into two stages: a pre-decoder block that generates intermediate test address signals and control signals from input address signals, and a signal generation block that decodes these intermediate signals to produce the final test mode signals. This segmentation allows exponential expansion of test mode signals while maintaining manageable wiring complexity at each stage.
Solution Approach 2:
The pre-decoder block acts as an intermediary between the input address signals and the final test mode signals. It generates intermediate test address signals and control signals that enable the signal generation block to produce exponentially more test mode signals than the original address signals would directly support, thereby reducing the need for extensive global lines.
2Quantity of substance
If the number of global lines is increased to generate more test mode signals, then more test modes can be checked, but layout margin decreases
Solution Approach 1:
By segmenting the signal generation into pre-decoder and signal generation blocks, the patent achieves exponential expansion of test mode signals without proportionally increasing the number of global lines. The intermediate signals serve as a compact representation that enables high fan-out with minimal wiring overhead, preserving layout margin.
Solution Approach 2:
The patent introduces an intermediate dimension of control signals and test address signals that enables exponential signal generation. Instead of directly routing N address signals to M test mode signals (where M >> N), the system uses an intermediate layer that operates in a different signal space, achieving the same functional result with reduced wiring complexity and better layout margin.
3Quantity of substance
If the number of address signals is increased to generate more test mode signals, then more test modes can be generated, but the circuit complexity increases
Solution Approach 1:
The patent segments the decoding function into two specialized blocks: a pre-decoder that handles address signal preprocessing and generates intermediate signals, and a signal generation block that performs the final decoding to produce test mode signals. This segmentation allows each block to be optimized for its specific function, reducing overall circuit complexity compared to a single large decoder.
Solution Approach 2:
The pre-decoder block performs preliminary decoding of the input address signals to generate intermediate test address signals and control signals before they are passed to the signal generation block. This preliminary action simplifies the work of the final decoder, reducing its complexity and enabling exponential signal generation with manageable circuit resources.
Data Source
AI summary
A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.