Test Mode Signal Generator for Semiconductor Memory

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Solution Overview

Problem

Conventional test mode signal generators for semiconductor memory devices require an increase in the number of addresses and chip size to support additional test modes, limiting their efficiency and scalability.

Innovation Solution

A test mode signal generator that increases the number of test modes without increasing the number of addresses or chip size, achieved through a test mode entry control unit, latch unit, and test mode register set signal generation unit, which shift, code, and latch signals to generate multiple test mode signals proportionally, allowing for more test modes without additional resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of test modes is increased in a conventional test mode signal generator, then the testing capability is improved, but the number of addresses and chip size must be increased

Engineering Contradiction:

Improvenumber of test modesVSAvoidchip size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple test mode signals into a single latched signal output. The latch unit latches multiple test address decoding signals and outputs them as a unified latched signal, which is then controlled by test entry mode signals to generate the final test mode signal. This merging approach allows multiple test modes to be supported without proportionally increasing chip size.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The latch unit serves multiple functions: it latches test address decoding signals, stores test entry mode signals, and generates test mode signals based on the combination of these signals. This multi-functionality allows the same hardware structure to support increased test modes without requiring additional dedicated circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the number of test modes is increased in a conventional test mode signal generator, then the testing capability is improved, but the number of addresses must be increased

Engineering Contradiction:

Improvenumber of test modesVSAvoidnumber of addresses

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent introduces a new dimension of test mode control by using test entry mode signals that operate independently from the traditional address-based control. Instead of solely increasing address bits to support more test modes, the invention adds a temporal dimension through multi-cycle test entry mode signal generation, allowing test modes to be selected through signal timing and combination rather than just address expansion.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the control parameter from purely address-based selection to a combination of latched address decoding signals and test entry mode signals. By modifying how test modes are selected and controlled, the system can support more test modes without proportionally increasing the address space, as the test entry mode signals provide additional control dimensions.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If the number of latch circuits is increased to support more test modes, then the test mode capacity is improved, but the chip size increases

Engineering Contradiction:

Improvetest mode capacityVSAvoidchip size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple latch operations into a single latch unit that handles multiple test address decoding signals simultaneously. Instead of requiring separate latch circuits for each test mode, the unified latch unit latches multiple signals and uses test entry mode signals to control their output, thereby supporting increased test mode capacity without proportionally increasing the number of latch circuits.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single latch unit performs multiple functions: it latches different test address decoding signals at different times, stores test entry mode signals, and generates various test mode signals based on the combination of these signals. This multi-functional design allows one latch unit to replace what would traditionally require multiple separate latch circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7881136B2Test mode signal generator for semiconductor memory and method of generating test mode signals

Publication Date: 2011.02.01 SK HYNIX INC

AI summary

A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses. A latch unit latches test address decoding signals in response to the test mode set signal, and outputs test mode signals by allowing the latched test address decoding signals to be controlled by the respective test entry mode signals. A test mode signal is generated for each test entry mode, so that the number of test modes is increased without increasing the number of addresses for supporting test modes.