Test Module Real-Time Fail Counter Reduces Memory

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Solution Overview

Problem

Conventional test apparatuses increase overall testing time by requiring data processing and storage of fail data after testing, leading to longer sampling intervals due to high memory capacity requirements for error rate calculations.

Innovation Solution

A test module with a pattern generating section, comparing section, fail counter, and control section that allows for real-time counting and storage of mismatches during testing, using a control section to manage counters and reduce memory capacity needs by calculating error rates directly from counter values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If fail data is stored in fail memory for post-processing, then error rate calculation is possible, but memory capacity requirements increase and sampling intervals lengthen

Engineering Contradiction:
Improveerror rate calculationVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The fail counter accumulates fail data in real-time during the pattern burst, performing the counting action beforehand rather than requiring post-processing of stored data. This preliminary action eliminates the need for large memory capacity to store all comparison results, as only the accumulated fail count needs to be stored.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention extracts only the essential fail count information from the comparison results and stores it in a compact fail counter, separating the critical measurement data from the full comparison history. This extraction approach reduces memory requirements while preserving error rate calculation capability.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If fail data is processed after testing using software, then error rate can be calculated, but overall testing time increases

Engineering Contradiction:
Improveerror rate calculationVSAvoidtesting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The fail counter operates continuously during the pattern burst, accumulating fail data in real-time without interruption. This continuous action eliminates the need for separate post-processing steps, maintaining uninterrupted testing flow and reducing overall testing time while still enabling accurate error rate calculation.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The fail counting is performed preliminarily during the pattern burst itself, rather than as a separate post-processing step. This preliminary accumulation of fail data allows error rate calculation to be prepared in advance, eliminating time-consuming software processing after testing.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If fail counters read values after pattern burst, then fail counts are obtained, but real-time fail data acquisition is not possible

Engineering Contradiction:
Improvedata acquisition timeVSAvoidreal-time monitoring capability
Core Design Contradiction:
Loss of timeVSEase of operation

Solution Approach 1:

The fail counter continuously accumulates fail data throughout the pattern burst, maintaining real-time readiness for data acquisition. This continuous counting operation enables immediate reading of current fail counts at any point during testing, providing both fast data acquisition and real-time monitoring capability.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8756465B2Test module and a test method for reading a number of fails for a device under test (DUT)
Publication Date: 2014.06.17 ADVANTEST CORP
  • US8756465B2 patent drawing
  • US8756465B2 patent drawing

AI summary

Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program.