Test Multiplexer Bypasses Reset Logic for Stuck-At Fault Detection
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Solution Overview
Problem
Current ATPG methods bypass the functional reset logic path, preventing comprehensive testing for manufacturing defects in integrated circuits, which limits the detection of stuck-at faults in this critical circuit component.
Innovation Solution
Incorporating a test multiplexer and set/reset logic to bypass the functional reset logic during ATPG, allowing separate testing of stuck-at faults at reset inputs and enabling the generation of additional patterns to test the functional reset logic path, thereby detecting faults in both the reset inputs and the functional reset logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ATPG bypasses the functional reset logic path, then test time is reduced and testing efficiency is improved, but the ability to detect stuck-at faults in the reset logic is lost
Solution Approach 1:
The patent divides the testing process into two independent parts: (1) ATPG testing that bypasses the functional reset logic path for efficient fault detection in other areas, and (2) a separate dedicated test sequence that specifically tests the reset logic path. This segmentation allows each testing method to be optimized independently - ATPG for speed and comprehensive coverage elsewhere, and dedicated reset testing for thorough fault detection in the reset path.
Solution Approach 2:
The patent applies preliminary action by first executing the ATPG test sequence to detect faults in the majority of the circuit, then subsequently executing a dedicated reset logic test sequence. This ensures that the reset logic is tested with specific test patterns designed to expose stuck-at faults, while the overall testing process maintains high efficiency through the initial ATPG phase.
2Reliability
If dedicated test sequences are added to test reset logic, then fault detection capability is improved, but device complexity increases
Solution Approach 1:
The patent makes the test multiplexer and test sequence generator universal by configuring them to handle multiple testing objectives: (1) routing test signals to different circuit locations, (2) generating both ATPG test patterns and dedicated reset test patterns, and (3) detecting faults in both the reset logic and other circuit areas. This multi-functionality reduces the need for separate dedicated hardware for each testing purpose.
Solution Approach 2:
The test multiplexer serves as an intermediary component that mediates between the test sequence generator and the circuit under test. It selectively connects test signals to different locations in the circuit based on the current test phase, enabling the same hardware infrastructure to support both ATPG testing and dedicated reset logic testing without requiring separate physical test paths.
Data Source
AI summary
A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.