Shielding Test-Off Lines to Block Capacitive Coupling
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Solution Overview
Problem
Semiconductor memory devices malfunction due to capacitive coupling between lines carrying test mode signals, leading to unintended entry into test mode or delays in exiting test mode, causing failures in data read/write operations.
Innovation Solution
Internal circuits are configured to perform test operations in response to test mode signals, and a test-off signal is used to disable these operations, with an off-signal transmission line being placed to minimize capacitive coupling effects, ensuring the test-off signal is less affected by parasitic capacitance, thereby preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If transmission lines for test mode signals are disposed between global data I/O lines to reduce capacitive coupling, then capacitive coupling effect between data lines is reduced, but the test mode signals are affected by capacitive coupling from data lines causing unintended test mode entry
Solution Approach 1:
A ground line is introduced as an intermediary between the data I/O lines and the test mode signal transmission lines. This ground line acts as a shield that blocks the capacitive coupling from the data lines to the test mode signals, preventing unintended test mode entry while maintaining the space-efficient arrangement of transmission lines between data lines.
Solution Approach 2:
The patent utilizes the ground line to convert the harmful capacitive coupling effect into a beneficial shielding effect. By placing the ground line between the data lines and test mode lines, the parasitic capacitance that would otherwise couple noise into the test mode signals is redirected to the ground, transforming the harmful interference into a protective barrier.
2Productivity
If more metal lines are disposed in a given space to achieve high integration, then device integration is improved, but capacitive coupling effect between lines increases
Solution Approach 1:
The patent addresses the capacitive coupling problem by introducing a vertical dimension to the line arrangement. Instead of only horizontal spacing between data lines and test mode lines, a ground line is inserted in between, creating a layered structure that effectively reduces capacitive coupling while maintaining high integration density in the planar layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes the operation of semiconductor memory devices by preventing unintended test mode entries and ensuring timely transitions out of test mode, even when test mode signals are affected by capacitive coupling.
Implementation Method 1
capacitive coupling between lines carrying test mode signals
Data Source
AI summary
Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.