Test Pad Formation Between Adjacent Transistor Regions
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Solution Overview
Problem
Current LTPS display technologies face low yield rates and challenges in achieving narrow frames due to the large occupied area of transistor regions and test pads, which hinder efficient array testing and high image resolution in mobile devices.
Innovation Solution
A method is introduced to form test pads between adjacent transistor regions on a glass substrate, where field-effect transistors are arranged at the fringe regions, and these pads are used to perform array tests by applying different voltage levels, allowing for reduced fringe region size and facilitating a narrower frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test pads are arranged at the adjacent fringe region of each transistor region, then array test can be performed, but the occupied area increases and narrow frame cannot be achieved
Solution Approach 1:
The patent merges the test pad structure with the data line structure by making the test pad share the same conductive layer and routing path as the data line. This integration allows the test pad to be formed within the existing data line space, eliminating the need for separate dedicated test pad areas and reducing the overall occupied area while maintaining array test functionality.
Solution Approach 2:
The patent changes the spatial arrangement by extending the test pad along the length direction of the data line rather than placing it perpendicular to the data line at the fringe region. This dimensional reorientation allows the test pad to utilize the longitudinal space of the data line, reducing the lateral occupation at the fringe region and enabling narrow frame design.
2Productivity
If De-Mux is adopted to increase array test efficiency, then testing capability is improved, but the required height for De-Mux and test pad becomes an obstacle to narrow frame
Solution Approach 1:
The patent extracts the array test functionality from the traditional De-Mux structure and integrates it directly into the data line and transistor gate structure. By taking out the separate De-Mux component and embedding the test function within the existing pixel circuit elements, the patent eliminates the additional height requirement that would be needed for a standalone De-Mux structure, thereby enabling narrow frame design while maintaining test efficiency.
Solution Approach 2:
The patent makes the data line and transistor gate structure serve multiple functions: they act as both the functional data transmission path during normal operation and as the test signal path during array testing. This multi-functionality eliminates the need for separate De-Mux hardware, reducing the overall height requirement while preserving array test capability.
Data Source
AI summary
The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.