Test Path Compensating Circuit for Signal Synchronization
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Solution Overview
Problem
In electronic devices, the varying lengths of electrical paths between test pads and a target circuit cause timing differences in test signals, leading to imprecise testing results, especially in scaled-down devices where these differences can significantly impede accurate testing.
Innovation Solution
A test path compensating circuit and system that utilize voltage-control delay circuits, controlled by control voltages generated from an external signal, to linearly adjust the delay amounts of input test signals, ensuring synchronized delivery of test signals to the target circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test signals are transmitted through multiple electrical paths of different lengths, then the test coverage is improved, but timing synchronization deteriorates
Solution Approach 1:
The patent applies preliminary action by introducing delay circuits before the test signals reach the target circuit. These delay circuits pre-adjust the timing of test signals based on their respective path lengths, ensuring that all test signals arrive at the target circuit simultaneously. This preliminary timing adjustment resolves the synchronization issue caused by different path lengths while maintaining comprehensive test coverage.
2Volume of moving object
If the electrical paths are scaled down to reduce device size, then the device compactness is improved, but the timing difference becomes more significant
Solution Approach 1:
The patent applies local quality by introducing different delay amounts for different test signal paths. Each delay circuit is configured with specific delay characteristics tailored to its corresponding electrical path length. This localized adjustment ensures that test signals from longer paths receive greater delay compensation, while signals from shorter paths receive minimal delay, thereby maintaining test precision in scaled-down devices.
3Loss of time
If delay circuits are introduced to synchronize test signals, then timing synchronization is improved, but circuit complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting the delay time parameter of delay circuits to achieve synchronization. Rather than introducing complex control mechanisms, the solution varies the delay time parameter according to each electrical path's characteristics. This parameter-based approach achieves timing synchronization with minimal additional circuitry, thereby limiting the increase in overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise control of delay amounts, compensating for path length differences and variations due to PVT changes, thereby improving the reliability and accuracy of test results by synchronizing input test signals across different paths.
Implementation Method 1
a plurality of voltage-control delay circuits electrically coupled to the plurality of electrical paths, respectively, and configured to control delay amounts of input test signals received from one or more of the plurality of test pads, based on one or more of the plurality of control voltages
Data Source
AI summary
A test path compensating circuit may include a plurality of electrical paths electrically coupling a plurality of test pads to a test target circuit. The test path compensating circuit may include a control voltage generation circuit configured to generate a plurality of control voltages. The test path compensating circuit may include a plurality of voltage-control delay circuits electrically coupled to the plurality of electrical paths, respectively, and configured to control delay amounts of input test signals received from one or more of the plurality of test pads, based on one or more of the plurality of control voltages, and provide output test signals to the test target circuit.