Test Pattern Count Prediction for Scan Configuration
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Solution Overview
Problem
Conventional test compression techniques for circuit testing are time-consuming and require brute force 'trial-and-error' methods to determine optimal test configuration, compromising analytical accuracy and increasing design complexity due to the need for careful selection of scan chains and input/output channels.
Innovation Solution
A method to predict pattern counts for test configuration determination, involving test pattern generation and encoding processes to minimize active input channels, using statistical analysis to determine the minimum acceptable number of input channels and assuming similar input data volumes for different channel numbers, and storing test pattern counts for various input channel configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If brute force trial-and-error technique is used to determine test configuration, then accurate test coverage and pattern count can be obtained, but the process becomes time-consuming
Solution Approach 1:
The patent performs preliminary test pattern generation and encoding for a limited number of input channel configurations before final selection. By pre-calculating pattern counts and coverage metrics for candidate configurations, the method avoids exhaustive trial-and-error while maintaining accuracy in determining the optimal test configuration.
2Manufacturing precision
If test pattern generation is performed for all possible configurations, then optimal test configuration can be found, but the complexity of the process increases
Solution Approach 1:
The patent segments the test configuration search space by evaluating only specific candidate input channel configurations rather than all possible combinations. The test compression analyzer is divided into modules that independently calculate pattern counts and coverage metrics for each candidate, reducing overall system complexity while maintaining optimization capability.
3Productivity
If fault sampling is used to reduce test pattern generation time, then productivity improves, but analytical accuracy is compromised
Solution Approach 1:
The patent applies partial action by performing test pattern generation for a selected subset of candidate input channel configurations rather than all configurations. This selective approach maintains analytical accuracy for the evaluated candidates while improving overall productivity by avoiding unnecessary calculations for configurations that will not be selected.
Data Source
AI summary
One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.