Test Pattern Generation for Semiconductor ICs
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Solution Overview
Problem
Existing test pattern generation methods for semiconductor integrated circuits fail to uniformly control temperature during testing, leading to inefficiencies in power consumption and heat generation, particularly due to spatial and temporal variations in power consumption, which can impact test accuracy and reliability.
Innovation Solution
A method that selects and optimizes test patterns using a computer to minimize power consumption variations across regions of the integrated circuit by determining optimal 'don't care' values, generating sequences with no 'don't care' bits to achieve spatial temperature uniformity, and rearranging test patterns to reduce temporal temperature variations without additional devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test patterns are applied to semiconductor integrated circuits during testing, then test coverage and defect detection are improved, but power consumption increases and temperature varies spatially and temporally
Solution Approach 1:
The patent segments the test pattern sequence into multiple groups and applies them in an optimized order. By dividing the test patterns and rearranging their sequence, the patent reduces peak power consumption and minimizes temporal temperature variations during testing, while maintaining comprehensive test coverage
Solution Approach 2:
The patent determines don't care values specifically for test patterns to minimize power consumption in regions that are not critical for defect detection. By selectively optimizing don't care bit values in non-critical regions, the patent reduces local power consumption and temperature without compromising test accuracy in critical areas
2Loss of energy
If don't care values are determined to reduce power consumption, then heat generation is reduced, but test pattern optimization complexity increases
Solution Approach 1:
The patent changes the parameters of test patterns by determining optimal don't care values. By systematically varying and optimizing these parameter values, the patent reduces power consumption and heat generation while managing the complexity through structured optimization approaches
3Reliability
If test patterns are applied to detect stuck-at faults and delay faults, then product reliability is improved, but test cost increases
Solution Approach 1:
The patent performs preliminary optimization of test patterns before actual testing by determining don't care values and arranging test pattern sequences in advance. This preliminary action reduces power consumption and temperature variations during testing, improving reliability while managing test system complexity through pre-computation
Data Source
AI summary
A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.