Test Pattern Structure for Semiconductor Interconnection Failure Detection
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Solution Overview
Problem
Conventional test pattern structures in semiconductor devices face challenges in quickly and accurately identifying failure interfaces in interconnection structures, particularly high contact or via resistance, which requires time-consuming cross-section SEM analysis and does not allow for effective wafer mapping of failure interfaces.
Innovation Solution
A test pattern structure comprising a first conductive layer and a second conductive layer connected through multiple interfaces, with terminals for resistance measurement, allowing for the identification of failure interfaces without SEM analysis, using conductive plugs and lines made from materials like metal, metal nitride, polysilicon, and polycide, and optionally including dielectric or underlying conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cross-section SEM is performed to identify failure interfaces, then measurement precision is improved, but loss of time increases significantly
Solution Approach 1:
The test pattern is divided into multiple serpentine structures, each containing specific interconnection elements (contact plugs, via plugs, metal lines) that can be independently tested. This segmentation allows targeted resistance measurement of different interconnection interfaces without requiring comprehensive SEM analysis of the entire wafer, thereby reducing testing time while maintaining identification accuracy.
Solution Approach 2:
The patent introduces test patterns with specific interconnection structures as intermediaries between the measurement system and the actual device interconnections. These test patterns serve as mediators that enable indirect but accurate assessment of interconnection quality through resistance measurements, avoiding the need for direct SEM observation while preserving measurement precision.
2Measurement precision
If cross-section SEM is used for failure analysis, then measurement precision is improved, but device complexity increases due to additional equipment requirements
Solution Approach 1:
The patent replaces the mechanical/physical SEM analysis system with an electrical resistance measurement system. Instead of using SEM equipment to visually inspect and identify failure interfaces, the invention uses simple resistance measurements through test patterns to detect and locate interconnection failures, thereby reducing equipment complexity while maintaining diagnostic capability.
3Measurement precision
If single-point SEM measurement is performed, then measurement precision at that point is improved, but productivity decreases due to inability to map failures across the wafer
Solution Approach 1:
The test pattern design provides multi-functionality: the same serpentine structure serves both as a localized failure detection mechanism and as a basis for wafer-wide mapping. By measuring resistance across multiple test patterns distributed on the wafer, the system simultaneously achieves local failure identification and global defect distribution mapping, thereby improving productivity without sacrificing local measurement precision.
Data Source
AI summary
A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.