Test Pattern Reordering for IC Fault Coverage

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Solution Overview

Problem

Current test pattern generation methods for integrated circuits do not efficiently reorder or remove test patterns to achieve higher fault coverage with fewer patterns, leading to suboptimal testing efficiency and increased data bandwidth.

Innovation Solution

The proposed solution involves reordering test patterns based on productivity indices, where test patterns with higher productivity indices are moved forward in the sequence, and those with lower indices are swapped with higher ones from adjacent groups, optimizing the test pattern set to achieve higher fault coverage with fewer patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If test patterns are applied in the original sequence generated by ATPG, then all faults can be detected, but the number of test patterns required is large and testing efficiency is low

Engineering Contradiction:
Improvefault coverageVSAvoidtesting efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the parameter of test pattern sequence by calculating productivity indices for each test pattern and reordering them in descending order of productivity. This resequencing ensures that test patterns with higher productivity (those that detect more previously undetected faults) are applied earlier, thereby achieving high fault coverage with fewer test patterns while maintaining comprehensive fault detection capability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If more test patterns are applied to achieve higher fault coverage, then more faults are detected, but data bandwidth and testing time increase

Engineering Contradiction:
Improvefault coverageVSAvoiddata bandwidth
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the parameter of test pattern quantity by evaluating the productivity index of each test pattern and selecting only those with high productivity values. By applying test patterns in descending order of productivity and stopping when target fault coverage is achieved, the method reduces the total number of test patterns required, thereby reducing data bandwidth requirements and testing time while maintaining effective fault detection

Inventive Principle:
Principle #35Parameter changes

3Productivity

If test patterns are reordered based on productivity indices, then testing efficiency improves, but the complexity of test pattern generation increases

Engineering Contradiction:
Improvetesting efficiencyVSAvoidtest pattern generation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by calculating the productivity index for each test pattern in advance, before actual testing begins. The productivity indices are computed and stored, and test patterns are pre-sorted in descending order of productivity. This preliminary preparation eliminates the need for complex real-time calculations during testing, as the reordering is performed once beforehand, thus improving testing efficiency without adding ongoing complexity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9411014B2Reordering or removal of test patterns for detecting faults in integrated circuit
Publication Date: 2016.08.09 SYNOPSYS INC
  • US9411014B2 patent drawing
  • US9411014B2 patent drawing
  • US9411014B2 patent drawing

AI summary

A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.