Semiconductor Test Pattern Structures for Resist Poisoning Control
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Solution Overview
Problem
The dual-Damascene process in semiconductor fabrication is prone to resist poisoning, leading to underdeveloped photoresist portions and overetching, resulting in short circuits between adjacent interconnects due to inadequate separation, which affects the formation of accurate circuit patterns.
Innovation Solution
Incorporation of test structures with varying pattern parameters in the dual-Damascene process to evaluate the effects of resist poisoning, allowing for the determination of appropriate distances between conductive components to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dual-Damascene process is used to form interconnects, then chip size is reduced and data reliability is improved, but resist poisoning occurs leading to underdeveloped photoresist portions and overetching
Solution Approach 1:
The patent applies preliminary action by performing an additional etching step before the main dual-Damascene etching process. This pre-etching creates a recessed region that compensates for the overetching that will occur during subsequent photolithography and etching steps, thereby preventing pattern accuracy degradation while maintaining the reliability benefits of the dual-Damascene process.
Solution Approach 2:
The patent implements preliminary anti-action by creating a compensatory recessed structure that counteracts the harmful overetching effect. The recessed region formed in advance serves as a buffer that prevents the photoresist pattern from being completely eroded during the main etching process, thus neutralizing the resist poisoning problem before it can cause manufacturing defects.
2Ease of manufacture
If photopatterning and dry etching are performed to form openings, then interconnect structures are created, but particles or ions from the dielectric base layer pass through and cause resist poisoning
Solution Approach 1:
The patent introduces an intermediary structure - a recessed region formed in the dielectric layer - that acts as a buffer zone between the conductive material and the photoresist pattern. This intermediary structure intercepts particles and ions from the dielectric base layer, preventing them from reaching and poisoning the photoresist during subsequent processing steps, thus eliminating the harmful effect while maintaining ease of manufacture.
3Quantity of substance
If the photoresist portion between openings is underdeveloped, then resist poisoning has occurred, but this results in overetching and corner reduction of the dielectric layer
Solution Approach 1:
The patent applies beforehand cushioning by creating a recessed region with reduced height in advance. This pre-formed cushion compensates for the corner reduction that would otherwise occur during etching. The recessed structure absorbs the excessive etching damage, preventing it from reaching and degrading the corners of the main dielectric layer, thus protecting the geometric integrity even when photoresist development is compromised.
4Volume of moving object
If adequate separation between conductive components is not maintained, then chip size is reduced, but short circuits occur between adjacent interconnects
Solution Approach 1:
The patent applies preliminary action by forming a recessed region between adjacent conductive components before the main interconnect formation process. This pre-formed separation structure ensures adequate electrical isolation is established in advance, allowing the chip size to be minimized while guaranteeing that short circuits between adjacent interconnects will not occur, thus resolving the contradiction between compactness and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the identification of suitable pattern parameters that minimize resist poisoning, ensuring proper separation of interconnects and preventing short circuits, thereby enhancing the reliability and accuracy of semiconductor device fabrication.
Implementation Method 1
The particles or ions of the basic substance 14 neutralize photo-generated acid of the photoresist 22
Implementation Method 2
The anti-reflective coating 21 minimizes intensity of light reflected from the coated surfaces
Implementation Method 3
A diffusion barrier layer and a seed layer of a conductive material (e.g., copper (Cu)) are deposited by a physical vapor deposition (PVD) method, such as sputtering
Implementation Method 4
deposited by a physical vapor deposition (PVD) method, such as sputtering
Implementation Method 5
The conductive material is further deposited by electroplating to fill the openings
Implementation Method 6
excess conductive material is removed by planarization, such as chemical-mechanical polishing (CMP)
Data Source
AI summary
Apparatuses and methods with controlled resist poisoning in manufacturing semiconductor devices are described. An example apparatus includes a first structure and a second structure. The first structure includes a first conductive component and a second conductive component adjacent to one another. The second structure includes a third conductive component and a fourth conductive component adjacent to one another. The third and fourth conductive components correspond to the first and second conductive components respectively. A first distance between the first conductive component and the second conductive component is different from a second distance between the third conductive component and the fourth conductive component.