Test Point Circuit Multi-Cycle Capture LBIST Area Overhead
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Solution Overview
Problem
In the context of Logic Built-In Self Test (LBIST) for semiconductor devices, the existing methods face challenges in detecting failures due to limitations in test data volume and execution time, leading to incomplete fault coverage and increased area overhead from the need for multiple test point insertions.
Innovation Solution
A test point circuit is designed to capture operation results across multiple capture clocks within a single clock sequential test period, reducing the number of test points required and minimizing area overhead while enhancing fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test point circuits are inserted to increase fault coverage in LBIST, then the detection capability improves, but the area overhead increases
Solution Approach 1:
The test point circuit is divided into multiple functional units: a capture unit with first and second flip-flops for capturing operation results at different clock cycles, a comparison unit for comparing captured values, and a test point insertion unit. This segmentation allows each unit to perform its function efficiently, reducing the overall area required while maintaining high fault coverage through multi-cycle capture capability.
Solution Approach 2:
The test point circuit is designed to perform multiple functions within a single structure: it captures operation results at different clock cycles, compares captured values to detect failures, and integrates with the scan chain for both normal operation and test modes. This multi-functionality eliminates the need for multiple separate test point circuits, reducing area overhead while maintaining comprehensive fault coverage.
2Reliability
If the number of shift cycles is increased to match the number of scan FFs, then complete test coverage is achieved, but the test time increases
Solution Approach 1:
The capture unit captures operation results in advance during the first capture clock cycle, storing them in the first flip-flop. This preliminary capture allows the comparison unit to immediately compare the captured value with the expected value without waiting for additional shift cycles, thereby achieving complete test coverage while reducing test time.
Solution Approach 2:
The test point circuit operates continuously across multiple clock cycles: the first flip-flop captures operation results at the first capture clock, the second flip-flop captures at the second capture clock, and the comparison unit continuously compares captured values with expected values. This continuous operation ensures complete test coverage without requiring extended test time.
3Measurement precision
If test data is stored in external tester memory for scan test, then test precision is maintained, but the tester memory capacity requirements increase
Solution Approach 1:
The test point circuit extracts and captures operation results directly from the circuit under test using internal flip-flops and comparison units. By taking out the test data capture and comparison functions from the external tester and implementing them internally, the circuit reduces the volume of test data that must be stored in external tester memory while maintaining test precision through immediate comparison of captured values with expected values.
Data Source
AI summary
It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.