Test Point Clock Gating for Lower IC Functional-Mode Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased power consumption by test point circuit elements in integrated circuits during functional mode operations due to ungated input clocks used for test point insertion is a challenge, as these elements continue to switch states despite not capturing or shifting out values, leading to excessive dynamic power dissipation.
Innovation Solution
Implementing a test point clock gating circuit element controlled by a test mode signal to gate the ungated input clock, coupled with a domain partitioner and domain matrix generator to identify and group test point circuit elements into clock and power domains for selective activation, reducing the number of clock gating elements and shared test mode signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test point circuit elements are inserted into the IC design for testing, then test coverage and testability are improved, but power consumption increases during functional mode operations
Solution Approach 1:
The patent applies preliminary action by inserting clock gating circuit elements into the IC design during the design phase, before fabrication. These gating elements are pre-configured to receive test mode signals that will control clock distribution to test point circuit elements during functional mode operations, thereby preventing unnecessary switching and reducing power consumption before the problem actually occurs
Solution Approach 2:
The patent implements dynamics by making the clock signal distribution to test point circuit elements dynamic and controllable through test mode signals. The clock gating circuit elements dynamically enable or disable clock signals based on operational mode, allowing the system to adapt its power consumption characteristics according to whether it is in test mode or functional mode, thus resolving the contradiction between maintaining testability and reducing operational power consumption
2Ease of operation
If ungated input clocks are used for test point circuit elements, then test point insertion and testing are simplified, but unnecessary switching and dynamic power dissipation occur during functional mode
Solution Approach 1:
The patent introduces clock gating circuit elements as intermediary components between the ungated input clock source and the test point circuit elements. These gating elements act as mediators that selectively block or pass clock signals based on test mode signals, thereby preventing the direct unnecessary switching that would occur with ungated clocks while maintaining the simplicity of test point insertion
Solution Approach 2:
The patent applies segmentation by dividing the clock distribution system into separate controllable segments. Each test point circuit element or group of elements receives clock signals through dedicated gating circuitry, allowing independent control of each segment's clocking based on test mode signals, thus enabling precise power management while maintaining ease of test point insertion
3Use of energy by moving object
If clock gating circuit elements are added to control test point clocks, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing clock gating circuit elements that serve multiple functions: they control clock distribution to test point circuit elements, respond to test mode signals, and enable power management during functional mode operations. This multi-functionality reduces the need for separate dedicated control circuits, thereby limiting the increase in device complexity while achieving power consumption reduction
Solution Approach 2:
The patent merges the clock gating functionality with the existing test mode signal generation infrastructure. The clock gating circuit elements are integrated into the design and share control signals with other test functions, combining multiple control functions into unified circuitry rather than adding separate independent control systems, thus reducing the net increase in device complexity
4Reliability
If test point circuit elements remain active during functional mode, then test readiness is maintained, but unnecessary switching and power consumption occur
Solution Approach 1:
The patent implements periodic action by using test mode signals that periodically enable or disable clock signals to test point circuit elements based on operational mode. During functional mode, clock signals are gated off periodically, allowing test point elements to remain ready for testing while preventing continuous unnecessary switching and improving power efficiency
Data Source
AI summary
The present disclosure relates to reducing power consumption of test point circuit elements of an integrated circuit (IC) design. An ungated input clock for at least one testing point circuit element for the IC design can be identified. The IC design can be updated by coupling a test point clock gating circuit element to a clock gate input node of the IC design that is to receive the ungated input clock, to the at least one test point circuit element, and to a test mode signal generation element that is to provide a test mode signal to create an updated IC design. The test point clock gating circuit element can be enabled and disabled based on a logical value of the test mode signal to control a supply of the ungated input clock to the at least one testing point circuit element.