Semiconductor Test-Point Access Structure for Precise FIB Probing
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Solution Overview
Problem
Existing focused ion-beam (FIB) tools lack sufficient spatial resolution and accuracy to access and probe smaller test-points on semiconductor wafers due to increasing chip complexity and congestion, while optical lasers cannot measure absolute voltages or I/V curves, necessitating a solution that allows precise access without damaging adjacent cells.
Innovation Solution
A test-point access structure is embedded in spare tiling regions of the semiconductor, using doped regions and target pads to guide FIB milling, enabling precise access to target test-points through voltage contrast imaging and mechanical probing, allowing existing FIB tools to reach smaller structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If FIB tools are used to access smaller test-points in advanced semiconductor nodes, then diagnostic capability is improved, but spatial resolution and milling accuracy deteriorate due to chip congestion
Solution Approach 1:
The patent introduces an intermediary structure consisting of a target pad and doped regions that mediate between the FIB tool and the target test-point. The doped regions generate detectable signals that serve as intermediaries to guide the FIB milling process, enabling accurate localization of small test-points without direct visualization, thus resolving the contradiction between accessibility and milling precision in congested chip layouts
Solution Approach 2:
The patent implements preliminary action by pre-configuring the test-point access structure with target pads and doped regions during semiconductor fabrication. This preparatory structure enables the FIB tool to subsequently locate and access test-points accurately without requiring high spatial resolution during the actual probing operation, thereby solving the precision-accessibility contradiction
2Ease of operation
If optical lasers are used for testing, then non-contact measurement is achieved, but absolute voltage and current measurement capability is lost
Solution Approach 1:
The patent merges the advantages of both contact and non-contact methods by combining the FIB tool's material removal capability with electrical contact measurement. The target pad structure allows the FIB to create a physical connection for accurate voltage and current measurements while maintaining the non-contact advantage of automated tool operation, thus resolving the contradiction between ease of operation and measurement precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables existing FIB tools to accurately access and measure absolute voltages at smaller test-points, ensuring compatibility with advanced CMOS nodes and preventing damage to adjacent circuits, thus enhancing failure analysis capabilities.
Implementation Method 1
a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool
Implementation Method 2
a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool
Implementation Method 3
the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal
Implementation Method 4
the CE tool is a focused ion-beam (FIB) device
Data Source
AI summary
One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.