Test-Point Flop Allocation for Physically Aware Circuit Layout
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Solution Overview
Problem
Modern circuit designs face inefficiencies due to extensive interconnect wiring between numerous test-point nodes and test-point flops, leading to increased material costs and space limitations in integrated circuits (ICs).
Innovation Solution
A test-point flop allocation module in an EDA application divides test-point nodes into sharing groups based on physical location, relocating flops to reduce interconnect wiring by grouping nodes proximally and optimizing their placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test-point nodes are distributed across the physical layout of the circuit, then test coverage is improved, but extensive interconnect wiring is required between test-point flops and test-point nodes
Solution Approach 1:
The patent segments test-point nodes into multiple groups based on their physical locations in the circuit layout. Each group is assigned to a dedicated test-point flop, creating localized test clusters. This segmentation reduces the global interconnect wiring requirement by limiting connections to local groups rather than requiring all-to-all connections across the entire circuit, thereby resolving the contradiction between comprehensive test coverage and extensive interconnect wiring.
2Area of stationary object
If the number of test-point flops is reduced through logical coupling, then device area is reduced, but interconnect wiring between remaining flops and nodes increases
Solution Approach 1:
The patent applies local quality by creating spatially localized test-point groups where each group contains test nodes that are physically close to each other in the circuit layout. Each localized group is served by a single test-point flop positioned near that group. This local organization reduces the overall number of flops needed while minimizing interconnect wiring length within each local cluster, resolving the contradiction between reducing device area and minimizing interconnect complexity.
3Device complexity
If test-point nodes are grouped into sharing groups based on physical location, then interconnect wiring is reduced, but relocation of flops is required
Solution Approach 1:
The patent performs preliminary action by automatically performing flop relocation during the design phase using EDA tools. The system analyzes the circuit layout, identifies optimal groupings of test nodes, and determines the best locations for placing test-point flops before fabrication. This preliminary optimization of flop positions based on physical node locations reduces interconnect wiring complexity while the automated nature of the process makes the relocation manageable and systematic rather than manual and error-prone.
Data Source
AI summary
A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.