Test Point Insertion for Circuit Fault Detection
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Solution Overview
Problem
Current circuit testing technologies face challenges in reducing test pattern counts due to complex clocking schemes, large combinational depths, and insufficient fault models, leading to inflated test sets that exceed storage capacity and increase testing time and cost, especially in embedded systems and automotive electronics.
Innovation Solution
The method involves determining and inserting test points based on internal signal conflicts to reduce test pattern counts by computing and adjusting test points until predetermined conditions are met, using conflict metrics to identify optimal locations for control and observation points, thereby reducing horizontal and vertical conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test point insertion techniques are used to improve fault detection likelihood, then fault coverage is improved, but test pattern counts remain inflated and storage requirements exceed tester capacity
Solution Approach 1:
The patent segments the test pattern generation process by identifying and addressing horizontal conflicts (within the same test pattern) and vertical conflicts (across multiple test patterns) separately through targeted test point insertion at different circuit locations, allowing independent optimization of each conflict type to reduce overall test pattern counts
Solution Approach 2:
The patent introduces test points as intermediary elements inserted at specific circuit locations to mediate between conflicting signal requirements. These test points act as control or observation points that resolve horizontal and vertical conflicts by providing additional signal paths or detection capabilities without requiring increased test pattern counts
2Quantity of substance
If more test points are inserted to reduce test pattern counts, then test data compression is improved, but hardware overhead and area penalty increase
Solution Approach 1:
The patent applies local quality by selectively inserting test points only at specific circuit locations where horizontal and vertical conflicts are identified, rather than uniformly distributing test points throughout the circuit. This targeted approach minimizes hardware overhead while achieving test pattern reduction at critical conflict points
Solution Approach 2:
The patent uses partial action by inserting a limited number of test points at strategically selected locations that address the most significant conflicts, rather than inserting test points throughout the entire circuit. This partial intervention is sufficient to reduce test pattern counts without incurring excessive hardware overhead
3Measurement precision
If computational methods are used to identify optimal test point locations, then test point effectiveness is improved, but computational complexity and identification cost increase
Solution Approach 1:
The patent segments the computational analysis into two distinct phases: identifying horizontal conflicts (within single test patterns) and identifying vertical conflicts (across multiple test patterns). This segmentation allows each phase to use optimized algorithms appropriate to its specific conflict type, reducing overall computational complexity while maintaining precision in test point location selection
Data Source
AI summary
Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.