Test Point Insertion Using Ungated Clock Inputs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic design automation (EDA) systems face challenges in achieving high test coverage and efficiency due to the gap between estimated and actual coverage improvement from test point insertion, particularly due to the impact of clock gating logic, which increases the number of patterns required for test point control, leading to inefficient test coverage and increased circuit area.
Innovation Solution
An enhanced test point insertion method that uses ungated clock inputs from earlier in the clock path to improve test point effectiveness, reducing the number of patterns needed for test coverage and ensuring that inserted test points are active during scan operations, thereby closing the coverage gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test points are inserted into the circuit design, then test coverage is improved, but circuit area increases
Solution Approach 1:
The patent changes the clock signal parameter from gated to ungated for test point operation. By modifying the clock control mode (from gated to ungated), the test points become active and effective without requiring additional circuit area for extra control logic. This parameter change resolves the contradiction by enabling test coverage improvement while avoiding additional area overhead.
2Use of energy by moving object
If clock gating logic is used in the circuit, then power consumption is reduced, but test point effectiveness decreases and more patterns are required
Solution Approach 1:
The patent implements dynamic clock control where the clock gating logic is selectively bypassed during test operations. The system dynamically switches between gated mode (for normal power-efficient operation) and ungated mode (for effective test point operation). This dynamic approach resolves the contradiction by maintaining power consumption benefits during normal operation while enabling effective test coverage when needed.
Solution Approach 2:
The patent changes the clock signal parameter from gated to ungated for test point operation. By modifying the clock control mode (from gated to ungated), the test points become active and effective without requiring additional circuit area for extra control logic. This parameter change resolves the contradiction by enabling test coverage improvement while avoiding additional area overhead.
3Reliability
If more test patterns are used to achieve high test coverage, then test coverage improves, but testing time and complexity increase
Solution Approach 1:
The patent extracts the clock gating control from the test point operation path. By removing the gating logic from the critical test signal path, test patterns can directly control test points without needing to first activate complex clock gating sequences. This extraction reduces the number of patterns required and decreases testing time while maintaining high test coverage.
Data Source
AI summary
Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.