Test Power-On-Reset Circuit for Secure IC Low-Voltage Testing
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Solution Overview
Problem
The reliability and security of integrated circuits are compromised during power-up testing due to the potential for the test POR input to override the power-on-reset (POR) circuit, allowing unauthorized access and tampering.
Innovation Solution
A skewed latch circuit within the test power-on-reset circuitry determines the configuration state of the integrated circuit, selectively disabling the POR circuit during secure operations to prevent unauthorized access and ensure secure testing by generating control signals that bypass the POR circuit only when the circuit is in a non-secure state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the test POR input is used to override the POR signal for testing power supply fluctuations, then the ability to test low-voltage operation is improved, but the security and reliability of the integrated circuit deteriorates due to potential unauthorized access
Solution Approach 1:
The patent applies local quality by making the test POR input's effect conditional rather than universal. The test input can only override the POR signal when specific local conditions are met: the integrated circuit must be in a predetermined operational state (determined by configuration bits) and the test input must be actively asserted. This localized control allows testing functionality to be enabled only where and when needed, preventing unauthorized override during normal operation while maintaining testing capability when properly configured.
2Productivity
If the test POR input overrides the POR signal to prevent initialization during voltage fluctuations, then the testing of power supply response is improved, but the potential for unauthorized operation override increases
Solution Approach 1:
The patent introduces configuration bits as an intermediary layer between the test POR input and the POR signal override function. These configuration bits act as a mediator that must be set to a predetermined value before the test input can affect the POR signal. This intermediary mechanism allows authorized testing to proceed efficiently when the circuit is properly configured, while preventing unauthorized access attempts by requiring knowledge of the specific configuration state, thus reducing the harmful factor of unauthorized operation override.
3Reliability
If the POR circuit is always active to ensure reset functionality, then the reliability of the integrated circuit is improved, but the ability to perform low-voltage testing deteriorates
Solution Approach 1:
The patent applies dynamics by making the POR circuit's responsiveness to the test input dynamic rather than static. The POR circuit maintains its reset functionality under normal conditions, but its behavior becomes dynamic when two conditions are simultaneously met: the integrated circuit is in the predetermined operational state (as determined by configuration bits) and the test POR input is asserted. This dynamic behavior allows the POR circuit to be overridden for low-voltage testing when appropriate, while maintaining reliable reset functionality during normal operation and when testing is not intended.
Data Source
AI summary
Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.