Test Probe Routing Engine for Semiconductor Wafer Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer test procedures, such as 100 percent wafer testing and wafer sample testing, face inefficiencies in reducing test probe travel and computation time, particularly when dealing with high-density semiconductor wafers, as they rely on serpentine raster sequences that do not optimize the total cost of travel effectively.
Innovation Solution
A routing engine and method that analyze alternative test probe routing sequences using representative circuit chips, employing heuristic analysis routines based on the Traveling Salesman Problem (TSP) to select and guide the test probe path, reducing overall travel distance and computation time through real-time and offline optimizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If serpentine raster sequence is used for test probe routing, then the routing path is simple to implement, but the total travel distance is not optimized
Solution Approach 1:
The routing engine performs preliminary analysis of alternative routing sequences using representative circuit chips before actual testing begins. By pre-calculating optimal paths based on wafer map data and circuit chip locations, the system establishes an optimized routing sequence in advance, avoiding the need to use simple serpentine patterns during actual testing.
Solution Approach 2:
The system dynamically adjusts the test probe routing sequence based on real-time wafer test data and identified defective regions. Instead of following a fixed serpentine pattern, the routing engine continuously optimizes the path by analyzing wafer maps and adjusting the sequence of circuit chips to be tested, adapting to the specific characteristics of each wafer.
2Measurement precision
If more circuit chips are tested per wafer map, then the representativeness of the wafer map improves, but the computation time increases
Solution Approach 1:
The system tests a selected subset of circuit chips rather than all chips on the wafer. By strategically choosing representative circuit chips that provide sufficient information about wafer quality, the system achieves adequate wafer map representativeness while significantly reducing computation time and test duration.
Solution Approach 2:
The wafer is divided into multiple wafer maps, each covering a specific region and testing a subset of circuit chips. The routing engine processes these segmented wafer maps independently, analyzing alternative routing sequences for each region separately. This segmentation allows parallel processing and reduces the computational burden compared to analyzing the entire wafer as a single unit.
Data Source
AI summary
Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one embodiment, the routing engine is for use with a test unit having at least one test probe and includes an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit. The routing engine also includes a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.