Test Processor Controls Chip Test Networks
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Solution Overview
Problem
Existing Design-for-Test (DFX) blocks in chips are inflexible, leading to significant engineering effort and schedule delays due to the need for extensive methodology and verification for small design changes, with limited ability to fix bugs or add features after tapeout.
Innovation Solution
Incorporating test processors to control and interface with test circuitry within chips, allowing for flexible programming and hierarchical organization to manage test networks, replacing the need for custom hardware-based DFX blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If custom hardware logic blocks (DFX blocks) are used for testing, then testing functionality is provided, but flexibility is reduced and engineering effort increases for design changes
Solution Approach 1:
The patent replaces custom hardware logic blocks (DFX blocks) with a processor-based system. Instead of using dedicated hardware circuits for testing, a general-purpose or specialized processor executes test instructions, allowing flexible configuration and modification of testing functionality through software rather than hardware changes.
Solution Approach 2:
The patent introduces a dynamic, reconfigurable testing system where the processor can be programmed with different test instructions to adapt to various testing scenarios. This allows the testing functionality to change dynamically without requiring physical hardware modifications, enabling post-tapeout bug fixes and feature additions.
2Reliability
If DFX blocks are updated during design cycle, then testing capabilities are improved, but design schedule is delayed due to extensive verification
Solution Approach 1:
The patent incorporates test processors and test instruction sets into the design from the beginning, along with the chip architecture. This preliminary integration allows for systematic testing capabilities to be established upfront, reducing the need for extensive later modifications and verification cycles.
Solution Approach 2:
The patent creates a universal processor-based testing platform that can handle multiple testing scenarios through different instruction sets. This multi-functional approach consolidates various testing capabilities into a single reconfigurable system, reducing the overall verification burden compared to multiple specialized DFX blocks.
3Reliability
If bug fixes or feature additions are made after tapeout, then product quality is improved, but this is limited with traditional DFX blocks
Solution Approach 1:
The patent enables dynamic reconfiguration of testing functionality through processor programming. After tapeout, bug fixes and feature additions can be implemented by loading new test instructions into the processor, providing continuous adaptability without requiring hardware re-spinning.
Data Source
AI summary
The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.