Test Scheduling via Pattern-Independent Channel Allocation
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Solution Overview
Problem
The increasing complexity and cost of testing system-on-chip (SoC) designs due to the difficulty in accessing embedded cores, long test development and application times, and large volumes of test data, particularly in three-dimensional integrated circuits, necessitate more efficient test scheduling and channel allocation methods.
Innovation Solution
The implementation of dynamic channel allocation and test scheduling methods that encode test data to require minimal core input channels, group test patterns based on core requirements, and allocate circuit channels independently of test data, using input and output switching networks with demultiplexers and OR gates for efficient channel utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If test data are allocated based on specific test patterns, then optimal channel usage for those patterns is achieved, but the design flow becomes complicated and requires knowing test patterns in advance
Solution Approach 1:
The patent implements dynamic channel allocation where the TAM configuration is determined after ATPG completion rather than being fixed in advance. This allows the system to adapt channel allocation based on actual test data requirements, optimizing channel utilization without complicating the earlier design flow stages.
Solution Approach 2:
The patent performs channel allocation as a preliminary step after ATPG but before actual test application. By determining the optimal TAM configuration based on generated test patterns beforehand, the system prepares an optimized test environment without requiring pattern-dependent design decisions during the design phase.
2Productivity
If more circuit channels are used for testing, then more cores can be tested in parallel, but the number of required circuit input and output channels increases
Solution Approach 1:
The patent applies compression techniques that process only the essential test data with high priority, allowing effective testing with a subset of available channels. This partial action approach enables parallel testing of multiple cores without requiring all possible channels to be actively used simultaneously.
Solution Approach 2:
The patent merges test responses from multiple cores through compression hardware that combines data from multiple sources into a reduced set of output channels. This merging capability allows multiple cores to be tested in parallel while using fewer physical output channels than would otherwise be required.
3Loss of time
If test patterns are compressed to reduce data volume, then data volume and test time are reduced, but additional on-chip hardware infrastructure is required
Solution Approach 1:
The patent introduces compression hardware as an intermediary component between the test pattern generator and the scan chains. This intermediary compresses test data in-place, reducing the volume of data that needs to be delivered through external channels and reducing test application time without requiring fundamental changes to the test architecture.
4Ease of operation
If dedicated TAMs are used for each core, then core access is simplified, but channel utilization efficiency decreases
Solution Approach 1:
The patent implements a universal TAM architecture where a shared set of test access channels serves multiple cores through dynamic allocation. The same physical channels can be allocated to different cores depending on which core is being tested, eliminating the need for dedicated channels per core while maintaining ease of access through software-controlled channel assignment.
Data Source
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AI summary
Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.