Test Socket Lead Contact Layout for Solderable Semiconductor Leads

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The reliability of connecting semiconductor device lead terminals to mounting substrates is compromised due to unevenness on the plated layer surface, which is exacerbated by high-temperature and high-current tests, leading to reduced wettability and connectivity issues.

Innovation Solution

The lead terminal design includes a protruding portion with a bending portion intersecting the surface, allowing the contact pin to engage with the lead bottom surface rather than the connecting portion, thereby minimizing surface unevenness and improving solder material wettability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the connecting portion of the lead terminal is pressed against the contact pin for electrical connection, then electrical connectivity is achieved, but unevenness are generated on the plated layer surface reducing solder wettability

Engineering Contradiction:
Improveelectrical connectivityVSAvoidplated layer surface uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The lead terminal is divided into distinct functional portions: a connecting portion for solder attachment to the mounting substrate, a protruding portion for contact with the contact pin, and a bending portion connecting them. This segmentation allows the contact pin to engage with the protruding portion rather than pressing on the connecting portion, preventing surface unevenness while maintaining electrical connectivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protruding portion extends in a direction intersecting the upper surface of the body, creating a three-dimensional configuration. This dimensional change positions the contact area away from the connecting portion, allowing electrical contact to be made at a different location and orientation, thus avoiding damage to the plated layer surface at the connecting portion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If high-temperature and high-current tests are performed to improve semiconductor performance, then testing capability is enhanced, but surface roughness of the plated layer becomes more conspicuous

Engineering Contradiction:
Improvetesting capabilityVSAvoidplated layer surface roughness
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The contact function is extracted from the connecting portion and assigned to a separate protruding portion. This extraction ensures that the mechanical and thermal stresses from high-temperature and high-current testing are applied to the protruding portion rather than the connecting portion, preventing exacerbation of surface roughness at the solder connection area.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of operation

If the contact pin is pressed against the connecting portion for testing, then electrical test can be performed, but reliability of connecting to mounting substrate is reduced

Engineering Contradiction:
Improveelectrical testingVSAvoidsolder connection reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The lead terminal is segmented into a connecting portion for reliable solder attachment and a protruding portion for contact pin engagement. This segmentation allows electrical testing to be performed on the protruding portion without compromising the integrity of the connecting portion, thereby maintaining both ease of operation and connection reliability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12429497B2Manufacturing method of semiconductor device and test socket for use in the same
Publication Date: 2025.09.30 RENESAS ELECTRONICS CORP
  • US12429497B2 patent drawing
  • US12429497B2 patent drawing
  • US12429497B2 patent drawing

AI summary

A manufacturing method of a semiconductor device includes a step of preparing a test object including a body for sealing a semiconductor chip and a lead terminal, a step of preparing a test socket including a first contact pin, and a step of electrically testing the semiconductor chip by contacting the first contact pin with the lead terminal. The lead terminal includes a lead upper surface located on an upper surface side of the body and a lead bottom surface located on an bottom surface side of the body. The lead terminal includes a protruding portion protruding from the body, and a connecting portion. The lead terminal further includes a bending portion that connects the protruding portion and the connecting portion. Then, in the electrical test step, the first contact pin is contacted with the lead bottom surface of the protruding portion.