Test Stimulus Generator for Complex Error Scenario Injection
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Solution Overview
Problem
Current computer processing system testing mechanisms are limited in generating and transmitting complex error scenarios, failing to accommodate the stringent requirements of simulating multiple errors within a fixed number of processor clock cycles, which hinders the comprehensive testing of error detection, correction, and recovery features.
Innovation Solution
A test stimulus generator that includes a pseudo-random number generator (PRNG) to calculate unique error scenarios and identify components within the system, using an initialization value and clock signal to generate and transmit complex error scenarios to various components such as CPU, memory, and adapters, allowing for both predetermined and random error simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If present testing designs use command control words to generate errors, then specific error scenarios can be injected into specific processor logic components, but the range and complexity of error scenarios that can be injected is limited
Solution Approach 1:
The patent employs a pseudo-random number generator (PRNG) that dynamically generates error scenarios based on seed values, allowing the testing mechanism to adaptively produce a wide variety of complex error scenarios without requiring pre-defined command sequences for each possible error condition
Solution Approach 2:
The patent introduces a new dimension of error scenario generation by using PRNG to create multi-dimensional error patterns that can simultaneously affect multiple processor components, moving beyond the traditional single-error-at-a-time approach of command control words
2Reliability
If multiple errors are injected simultaneously to test complex scenarios, then comprehensive error handling can be verified, but the testing mechanism cannot accommodate the stringent requirements of fixed clock cycle timing
Solution Approach 1:
The patent pre-generates error scenarios using PRNG before injection, allowing the system to prepare complex multi-error sequences in advance and inject them at precise clock cycle intervals without real-time computation delays
Solution Approach 2:
The patent uses PRNG to create replicated error patterns that can be injected simultaneously across multiple processor components, effectively copying error scenarios to multiple targets while maintaining precise timing control through the clock signal synchronization
3Adaptability or versatility
If command sequences are used to inject specific errors, then expected errors can be generated, but unexpected errors and rare exception cases cannot be adequately tested
Solution Approach 1:
The patent implements a self-service testing mechanism where the PRNG autonomously generates diverse error scenarios including rare exception cases without requiring manual design of command sequences for each possible error condition, simplifying the testing operation while maximizing error scenario variety
Data Source
AI summary
A test stimulus generator generates error irritations, or error sequences, within a processor system. The test stimulus generator includes an initialization register, a pseudo-random number generator (PRNG), a clock subsystem, and an output register. The PRNG calculates an output value from an initialization value stored in the initialization register. The PRNG output value represents a unique error irritation and identifies one or more components within the processor system to handle the error irritation. The clock subsystem generates either a continuous or pulsed clock signal that transfers the initialization value into the PRNG. The output register stores the PRNG output value and transmits the corresponding error irritation to the processor components identified to handle the error irritation. The test stimulus generator generates error irritations in a predetermined or random order based on the initialization value. A corresponding method and computer program product are also disclosed.