Test Structures for Interconnect Impedance Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current test structures for field-effect transistors and Kelvin field-effect transistors are inadequate for effectively testing manufacturing variations, particularly in contacts and vias, which hinders the identification of impedance and resistance variations.
Innovation Solution
A test structure is developed with multiple metallization levels, including interconnect lines and test pads, that directly connect source/drain regions with metallization lines, allowing for impedance measurement without passing through overlying interconnects, thereby minimizing interference from these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test structures use conventional interconnect paths through multiple metallization levels, then comprehensive testing of interconnect structures is achieved, but measurement accuracy deteriorates due to interference from overlying interconnects and via resistance
Solution Approach 1:
The test structure is segmented into separate functional components: current leads for supplying current, sense connections for measuring voltage drop, and distinct test structures for different measurement purposes. This segmentation allows the sense connections to be positioned optimally near the target impedance without being contaminated by overlying interconnect resistance, thereby improving measurement precision while maintaining manageable complexity through modular design
Solution Approach 2:
Sense connections act as intermediary elements that bridge the measurement system and the target impedance. These sense connections are specifically positioned in proximity to the target impedance and are designed to measure voltage drop without carrying significant current, thereby eliminating the influence of overlying interconnect resistance on the measurement and achieving accurate impedance determination
2Reliability
If test structures are formed later in the fabrication process, then more complete device structures are available for testing, but manufacturing time and cost increase
Solution Approach 1:
Test structures are formed as part of the initial metallization processing steps rather than as a separate later operation. The current leads and sense connections are integrated into the first and second metallization levels respectively, allowing test structures to be prepared in advance alongside the main device interconnects. This preliminary action enables testing to be performed earlier in the fabrication sequence without sacrificing testing completeness, thereby reducing overall manufacturing time
3Adaptability or versatility
If multiple metallization levels are used in test structures, then comprehensive interconnect testing is enabled, but the impact of overlying metallization on impedance measurement increases
Solution Approach 1:
The test structure employs local quality differentiation where the sense connections are positioned specifically in proximity to the target impedance in the first metallization level, while current leads are positioned in the second metallization level. This spatial differentiation ensures that the voltage measurement occurs locally near the target impedance before current passes through overlying interconnects, thereby maintaining measurement precision while enabling comprehensive testing through the multi-level structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accelerates testing and reduces fabrication costs by enabling earlier identification of failures in CMOS chip production, providing more accurate resistance measurements and reducing the impact of overlying metallization layers on impedance determination.
Implementation Method 1
Current is supplied via a pair of connections (i.e., current leads) to the test structure and a voltage drop occurs that allows the impedance (e.g., resistance) to be measured according to Ohm's law
Data Source
AI summary
Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.