Test Substrate Lithography Data Generation for Semiconductor Testing
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Solution Overview
Problem
Existing test substrate manufacturing methods face challenges in accurately testing semiconductor chips due to large general test circuits required for each channel, leading to increased size and signal transmission losses, and the use of BIST circuits reduces operational area on semiconductor chips.
Innovation Solution
A test substrate manufacturing apparatus and method that utilizes a test circuit database, definition information storing section, and lithography data generating section to select and position test circuits on the substrate based on device pad arrangements and testing content, enabling efficient formation of test circuits with reduced size and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general test circuit is provided for each channel to test a variety of semiconductor chips, then the testing versatility is improved, but the total area of the test circuits increases
Solution Approach 1:
The test substrate is divided into multiple regions, with each region containing a dedicated test circuit for specific testing functions. This segmentation allows different test circuits to be distributed across the substrate, reducing the area required for each individual circuit while maintaining overall testing versatility through the combined functionality of all regions.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of test circuits to a three-dimensional structure by forming test circuits on both the front surface and back surface of the test substrate. This dimensional change effectively doubles the available area for test circuits without increasing the substrate footprint, thereby maintaining versatility while reducing the area per circuit.
2Measurement precision
If the test circuit is provided on a probe card or adjacent substrate to decrease signal transmission distance, then the signal transmission accuracy is improved, but the space available for forming test circuits is limited
Solution Approach 1:
The patent utilizes both surfaces of the test substrate to form test circuits, effectively transitioning from a single-sided to a double-sided configuration. This dimensional approach provides ample space for complex test circuits while maintaining proximity to the probe card, thereby ensuring both sufficient circuit area and short signal transmission distances for high accuracy.
Solution Approach 2:
The patent combines multiple test circuits for different testing functions into a single integrated test substrate that is adjacent to the probe card. This merging of multiple circuits into one compact structure provides sufficient space for all necessary test circuits while maintaining close proximity to the devices under test, achieving both area efficiency and signal transmission accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate testing of semiconductor chips with reduced test circuit size, maintaining operational area on semiconductor chips and minimizing signal transmission losses, while enabling high-density circuit formation on the test substrate.
Implementation Method 1
manufacturing the test substrate by performing electron beam lithography on a semiconductor wafer based on the generated lithography data
Data Source
AI summary
A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information.