Test System Segmentation for Semiconductor DUT Redundancy Analysis
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Solution Overview
Problem
Conventional test apparatuses for semiconductor devices face challenges in efficiently processing large numbers of DUTs due to varying calculation loads, leading to increased costs and development time, with poor CPU compatibility and frequent design changes required to keep up with improving semiconductor technology.
Innovation Solution
A test system architecture that separates real-time FM control operations from redundancy analysis processing, using a pin electronics module connected via Ethernet to a general-purpose server, allowing for flexible distribution of calculation load and reducing the need for dedicated drivers or interface redesign, with the ability to dynamically assign cores and resources for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test apparatuses use dedicated CPUs for redundancy analysis, then real-time control operations can be performed, but calculation load varies significantly leading to increased costs and development time
Solution Approach 1:
The system separates real-time control operations from redundancy analysis operations by using different processing resources. The pin electronics module handles real-time control while the server handles redundancy analysis, dividing the workload to optimize both real-time performance and cost-effectiveness.
Solution Approach 2:
The patent introduces a server as an intermediary between the pin electronics module and the redundancy analysis process. This mediator handles the computationally intensive redundancy analysis tasks, allowing the pin electronics module to focus on real-time control without being burdened by varying calculation loads.
2Productivity
If dedicated interface designs are used for each semiconductor device generation, then optimal performance is achieved, but design changes are frequently required increasing development time
Solution Approach 1:
The patent employs Ethernet as a universal communication interface between the pin electronics module and the server. This standardized interface can handle various semiconductor device types and generations without requiring redesign, providing both optimal performance and adaptability to changing device specifications.
3Productivity
If high-performance CPUs are used to handle peak calculation loads, then all DUTs can be processed efficiently, but costs increase significantly
Solution Approach 1:
The system dynamically distributes processing tasks between the pin electronics module and the server based on workload requirements. The server handles computationally intensive redundancy analysis tasks that do not require real-time processing, allowing the use of cost-effective processing resources while maintaining high overall productivity.
4Device complexity
If multiple functions are integrated into a single CPU board, then device complexity is reduced, but calculation load on individual CPUs increases
Solution Approach 1:
The patent segments the system into distinct functional modules: the pin electronics module for real-time control and the server for redundancy analysis. This segmentation distributes the calculation load appropriately, preventing any single CPU from becoming overloaded while maintaining system simplicity through clear functional separation.
Data Source
AI summary
At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple fail memory in a real-time manner, temporarily stores fail information stored in the multiple fail memory, performs data processing on the fail information, and transfers the fail information thus processed to the general-purpose server. Each general-purpose server is controlled according to a computer program so as to perform redundancy analysis for a DUT based on the data received from the PE module.