Test TSV Conductive Protrusion for Semiconductor Package Testing
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Solution Overview
Problem
The challenge in testing memory chips with small bump sizes and high pitch density makes probe testing difficult in multi-chip semiconductor packages, particularly in vertical configurations using through-silicon vias (TSVs).
Innovation Solution
A semiconductor chip and package design that includes a conductive protrusion electrically coupled to a test TSV, positioned at the edge of the substrate, allowing for effective electrical coupling and testing, along with a method for manufacturing this design involving the formation of a land portion and conductive protrusion using a solder ball and reflow process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-chip package with vertical configuration and TSVs is used to increase storage capacity, then the storage density is improved, but the testing of memory chips becomes difficult due to small bump sizes and high pitch density
Solution Approach 1:
The invention segments the testing function by introducing a dedicated test TSV separate from the regular signal TSVs. This test TSV is specifically designed for testing purposes and is electrically coupled to a conductive protrusion that extends to the chip surface, allowing independent access to circuit nodes for testing without interfering with the dense signal bump array.
Solution Approach 2:
The conductive protrusion acts as an intermediary element between the test TSV and the external testing equipment. It provides a accessible test point on the chip surface that can be probed by external test equipment, serving as a mediator that bridges the internal circuit nodes (accessible only through TSVs) and the external test environment.
2Manufacturing precision
If the bump size and pitch are reduced to achieve fine pitch multi-chip package, then the device density is improved, but the probe testing capability deteriorates
Solution Approach 1:
The invention applies local quality by creating a specialized test region with a conductive protrusion that has different properties from the regular bump array. The protrusion is positioned at a specific location (edge of substrate) and has a larger effective probe area, making it locally optimized for testing purposes while the rest of the chip maintains fine-pitch bump structure for high-density interconnection.
Solution Approach 2:
The conductive protrusion extends in the vertical dimension from the chip surface, creating a three-dimensional test access structure. This vertical extension provides a taller, more accessible target for probe contact compared to flat or low-profile bumps, effectively adding a height dimension to the test interface that facilitates easier probing despite the fine pitch of surrounding bumps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable testing of circuit layers in each package product with fine pitch accuracy, facilitating the assembly and testing of multi-chip semiconductor packages, particularly in vertical configurations with TSVs.
Implementation Method 1
performing a reflow process such that the solder ball is fused to the first test TSV
Data Source
AI summary
A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.