Test Vector Generation Using Executable Verification Plan
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Solution Overview
Problem
Current methods for integrated circuit chip design verification are manual, time-consuming, and prone to generating repeated test vectors across machines and regressions, failing to efficiently handle multi-configuration chips and large state spaces.
Innovation Solution
A system and method for automatically generating unique test vectors using an Executable Verification Plan (EVP) and a Distributed Configuration Management System (DCMS) server, which optimizes data structures, customizes verification plans, and eliminates vector duplication by mapping and decoding data packets across Execution PCs, ensuring no overlap and efficient functional verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If manual constraint random verification is used, then verification can be performed with existing tools, but the process requires user intervention and consumes a lot of time
Solution Approach 1:
The system performs self-service by automatically generating test vectors without requiring user intervention. The constraint solver and verification engine operate autonomously, with the system itself managing the entire verification process from constraint definition to vector generation and coverage analysis.
Solution Approach 2:
The system performs preliminary action by pre-defining constraints, coverage criteria, and verification rules before the actual test vector generation. The executable verification plan is prepared in advance, allowing the system to efficiently generate vectors without requiring intermediate user input or decision-making.
2Extent of automation
If constrained random verification is used, then test vectors can be generated automatically, but repeated vectors are generated across machines and regressions
Solution Approach 1:
The system implements feedback mechanisms where test vector results from previous regressions and machines are fed back into the constraint solver. This feedback loop allows the system to learn from past executions and generate novel vectors that have not been previously tested, ensuring uniqueness across multiple regression cycles.
Solution Approach 2:
The system adds another dimension to vector generation by incorporating a uniqueness tracking mechanism that operates across the entire regression history. Instead of generating vectors in isolation, the system tracks vector identifiers and ensures each new vector is unique across all previous executions, effectively adding a temporal dimension to the generation process.
3Reliability
If multiple regression runs are performed to cover entire state space, then coverage is improved, but the process becomes more complex and time-consuming
Solution Approach 1:
The system achieves universality by creating a single executable verification plan that can be executed across multiple machines and regression runs. This universal plan encapsulates all necessary constraints, coverage criteria, and generation rules, allowing the same verification logic to operate consistently across different execution contexts without requiring separate configurations for each regression.
Solution Approach 2:
The system segments the verification process into distinct modular components: constraint definition, vector generation, execution, and coverage analysis. Each component is independently manageable and can be executed in sequence across multiple regressions, reducing overall system complexity while maintaining comprehensive coverage through systematic progression.
4Reliability
If user intervention is required at regular intervals, then verification can be monitored, but productivity decreases
Solution Approach 1:
The system performs self-service by automatically monitoring verification quality through built-in coverage tracking and constraint validation mechanisms. The system itself checks whether verification goals are being met and adjusts vector generation parameters accordingly, eliminating the need for external user intervention while maintaining high verification standards.
Solution Approach 2:
The system ensures continuity of useful action by maintaining uninterrupted automated verification processes. The executable verification plan runs continuously across multiple regressions without requiring user intervention, ensuring that quality monitoring and vector generation proceed without breaks or manual resets, thereby maximizing productivity while preserving reliability.
Data Source
AI summary
The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.