Test Vector Toggle Count Analysis for Scan Chain Power Estimation
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Solution Overview
Problem
Current methods for calculating toggle activity during scan-based testing of integrated circuits are inefficient, leading to inaccurate power dissipation estimates and potential false defects due to thermal and IR drop issues, especially with unbalanced scan chains and the presence of inverters.
Innovation Solution
An approach that analyzes load and unload vector data to quickly and accurately calculate toggle counts at each test clock pulse, eliminating the need for explicit scan shift simulation and accounting for scan chain structure, padding bits, and inverter effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan shift simulation is performed to calculate toggle counts, then accurate toggle information is obtained, but computation time increases significantly (proportional to square of scan chain length)
Solution Approach 1:
The patent segments the toggle count calculation into two independent components: load toggles (from load vector transitions) and unload toggles (from unload vector transitions). This segmentation allows each component to be calculated separately using efficient algorithms rather than full simulation, reducing computation time from O(L²) to O(L) where L is scan chain length, while maintaining accuracy.
Solution Approach 2:
The patent performs preliminary analysis of load and unload vectors to identify transition positions and patterns before calculating toggle counts. By pre-processing the vector data to mark transition locations and accounting for scan chain structure (including unbalanced chains and padding bits), the method avoids redundant simulation steps and directly computes accurate toggle counts.
2Productivity
If gross estimate techniques are used to calculate test power, then computation is faster, but accuracy deteriorates (does not account for scan chain structure, unbalanced chains, padding bits, and inverters)
Solution Approach 1:
The patent applies local quality by considering the specific structure of each scan chain, including unbalanced chain lengths, positions of inverters, and padding bits. Rather than using a uniform estimation approach, the method tailors the toggle count calculation to account for local variations in scan chain configuration, ensuring accurate power dissipation estimates for each specific design scenario.
Solution Approach 2:
The patent introduces intermediate data structures and analysis steps that capture the scan chain structure, inverter positions, and vector characteristics. These intermediates serve as mediators between the raw test vectors and the final power calculation, enabling accurate accounting of all factors (including overlapped scan effects) without requiring full simulation.
3Reliability
If higher test power is used to ensure adequate signal levels, then testing reliability improves, but thermal hot-spots and IR drops increase causing false defects
Solution Approach 1:
The patent uses toggle count analysis to provide feedback on power dissipation characteristics of test vectors. By calculating accurate toggle counts and identifying vectors with high switching activity, the method enables selection of test vectors that achieve adequate testing reliability while minimizing power dissipation, thus avoiding thermal hot-spots and IR drops that cause false defects.
Data Source
AI summary
A system, method, and computer program product is disclosed that recycle digital assertions for analyzing the test vectors to quickly and accurately calculate the switching activity at each test clock pulse or scan cycle. According to some approaches, load vector data and unload vector data are analyzed to determine toggle counts and switching activity, without requiring simulation to be performed.