Test Vias Extending Into STI Regions for Void Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device processing is detecting void formation and subsequent metal stringer shorts above shallow trench isolation (STI) regions, which are more prone to voiding due to high aspect ratios and pinching of protection layers, leading to inefficient detection of shorts between via contact holes.
Innovation Solution
A test structure and method involving a matrix of vias that extend at least to the edge of active areas and into STI regions, allowing for the detection of metal stringers through short-circuiting of test vias by voids in STI regions, while ensuring no shorts in active areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If vias are confined within active areas only, then detection of stringer shorts in active areas is achieved, but void formation in STI regions cannot be detected
Solution Approach 1:
The patent extends the via structure from the traditional two-dimensional confinement within active areas into the third spatial dimension by allowing vias to extend laterally into STI regions. This dimensional expansion enables the detection system to cover both active areas and STI regions, resolving the contradiction between precise detection within active areas and comprehensive detection coverage across the entire device structure.
Solution Approach 2:
The patent segments the detection function by creating different via configurations for different regions: vias in active areas maintain traditional confinement for precise local detection, while vias extending into STI regions provide broader coverage. This segmentation allows each via type to optimize its detection capability for its specific region while collectively providing comprehensive detection across the entire device.
2Reliability
If protection layers are conformally deposited over gate and spacer structures, then device protection is achieved, but voids form above STI regions due to pinching
Solution Approach 1:
The patent performs preliminary detection by forming test vias that extend into STI regions before the actual device fabrication is completed. This allows void formation to be detected early in the process, enabling corrective actions to be taken before subsequent processing steps are performed, thus preventing the propagation of defects through the manufacturing process.
Solution Approach 2:
The patent introduces test vias as intermediary structures that mediate between the protection layer deposition process and the final device quality assessment. These test vias serve as probes that interact with void formations in STI regions, providing indirect detection of manufacturing defects without interfering with the actual device structures.
3Productivity
If metal fill material is deposited to fill via contact holes, then via formation is completed, but stringers form that short adjacent vias when voids are present
Solution Approach 1:
The patent implements a feedback mechanism where test vias extending into STI regions provide information about void formation tendencies in the manufacturing process. This feedback allows process parameters to be adjusted to prevent void formation, thereby preventing stringer formation during metal fill deposition and maintaining via isolation reliability.
Solution Approach 2:
The patent performs preliminary detection of void formation-prone conditions using test vias before the metal fill deposition step. By identifying potential stringer formation risks early, the process can be adjusted to prevent stringer formation during the actual via filling operation, ensuring via isolation is maintained.
Data Source
AI summary
A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.