Testable Delay Selector Circuit for Accurate TDC Measurement
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in accurately measuring propagation delay degradation due to untestable delay selectors, particularly in serial TDCs, which lack testability and result in incorrect or misleading measurements, while parallel TDCs have a higher hardware overhead.
Innovation Solution
The design incorporates testable time-to-digital converters using 2-input multiplexers and inverters, allowing for the testing of faults in delay selectors by controlling the delay with single control bits and adjusting propagation delays, reducing hardware overhead through hybrid TDC implementations that combine serial and parallel designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial TDC architecture is used, then hardware overhead is reduced, but testability of delay selector deteriorates
Solution Approach 1:
The delay selector is segmented into multiple 2-input multiplexers arranged in a tree structure, where each multiplexer can be independently tested. This segmentation allows testability to be achieved without significantly increasing hardware overhead, as the modular structure reuses the basic multiplexer unit efficiently.
Solution Approach 2:
Inverters are introduced as intermediary elements between multiplexer inputs and outputs. These inverters enable test signal propagation through the delay selector by creating controllable signal paths, thereby improving testability without adding substantial hardware complexity.
2Measurement precision
If delay selector is made testable with additional components, then measurement accuracy improves, but hardware overhead increases
Solution Approach 1:
The testable delay selector merges the functionality of delay selection with test capability by integrating inverters and multiplexers into a unified structure. This combination achieves both measurement accuracy and testability without requiring separate test hardware, thereby controlling hardware overhead.
Solution Approach 2:
The delay selector structure is designed to be universal, serving both normal operation and test functions through the same hardware components. The multiplexers and inverters perform dual roles: signal routing during normal operation and test signal propagation during testing, eliminating the need for dedicated test hardware.
3Reliability
If 2-input multiplexers with inverters are used in delay selector, then testability improves, but device complexity increases
Solution Approach 1:
The delay selector employs dynamic control through select signals that route test or normal operation signals through the multiplexer network. This dynamic behavior allows the same hardware structure to adapt between test and operational modes, managing complexity through functional flexibility rather than structural multiplication.
Data Source
AI summary
A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.