Scalable Formal Coverage Analysis for Testbench Gates
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Solution Overview
Problem
Formal coverage analysis tools for testbenches require customized verification algorithms, leading to scalability limitations and increased runtime, making them inefficient for testbenches with formally proven property sets.
Innovation Solution
Applying scalable formal coverage analysis by selecting and mutating gates in the testbench, introducing mutation properties to determine coverage without requiring customized algorithms, using mutation selection logic and random value mutations to assess gate coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal coverage analysis tools are used to determine gate coverage in testbenches, then coverage evaluation capability is improved, but runtime increases and scalability is limited
Solution Approach 1:
The patent creates a copy of the original testbench and modifies it by introducing mutations at selected gates. This copied and mutated testbench is then used for coverage evaluation instead of analyzing the original testbench directly, enabling efficient coverage determination without exhaustive formal analysis of the complete original design.
Solution Approach 2:
The patent segments the coverage evaluation process by selecting specific gates for mutation and creating separate mutation properties for each mutated gate. This segmentation allows the verification tool to focus on evaluating coverage for individual gates independently, rather than performing a single comprehensive analysis of all gates simultaneously.
2Measurement precision
If formal coverage analysis tools are used to determine gate coverage in testbenches, then coverage evaluation capability is improved, but device complexity increases due to customized verification algorithms
Solution Approach 1:
The patent applies universal mutation operations that can be used across different gates and testbench configurations. The same mutation framework and property evaluation approach works for any gate in the design, eliminating the need for customized verification algorithms for each specific gate or design type.
Solution Approach 2:
The patent changes the state of selected gates by introducing mutations (parameter change) and uses this transformation to infer coverage information. By modifying gate behavior through mutation and observing property hittability, the system determines coverage without requiring complex specialized verification algorithms.
3Productivity
If gate mutation and property introduction are used to determine coverage, then scalability is improved, but testbench complexity increases
Solution Approach 1:
The patent performs preliminary gate selection and mutation before the actual coverage evaluation process. By pre-selecting gates and introducing mutations in advance, the system prepares the testbench for efficient coverage analysis, reducing the computational burden during the actual verification phase and improving overall scalability.
Solution Approach 2:
The patent introduces mutation properties as intermediary elements between the mutated gates and the coverage evaluation process. These mutation properties serve as mediators that capture the effect of gate mutations and enable the verification tool to assess coverage without directly analyzing the complex interactions of the original testbench logic.
Data Source
AI summary
A computer-implemented method, system, and computer program product for applying scalable formal coverage analysis to a testbench. A set of properties proven unhittable in an original testbench is selected to be considered for coverage analysis. A gate (e.g., latch) of a device under test is selected and mutated, where the mutation includes utilizing a random value and where a mutation property for the set of selected properties proven unhittable is associated with the mutated gate of the device under test. It is then determined whether the mutation property is hittable or unhittable while the gate is mutated in order to determine whether the gate is covered by the selected properties. A gate is covered by the selected properties if the mutation property is hittable while the gate is mutated. Furthermore, a gate is uncovered by the selected properties if the mutation property is unhittable while the gate is mutated.