Testbench Partitioning for Parallel Hardware Emulation
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Solution Overview
Problem
Current simulation acceleration methods face bottlenecks due to sequential processing in simulators, limiting the performance gains from concurrent requests between hardware and simulation platforms, especially when behavioral code cannot be synthesized for hardware prototyping.
Innovation Solution
The system dynamically partitions a testbench into multiple independent components that can run concurrently, mapping these components to corresponding hardware transactors, allowing parallel execution on a hardware emulation system, thereby overcoming sequential processing bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-threaded simulation system is used to execute testbench code, then the system complexity is low and ease of operation is maintained, but the productivity and speed are severely limited due to sequential processing
Solution Approach 1:
The testbench is divided into multiple independent partitioned testbenches, each capable of being executed separately. This segmentation allows the simulation workload to be distributed across multiple threads or processes, thereby increasing productivity while managing complexity through modular organization
Solution Approach 2:
The system transitions from single-threaded sequential execution to multi-threaded parallel execution by adding the dimension of concurrency. Multiple testbench partitions are executed simultaneously in different threads, fundamentally changing the execution model from sequential to parallel to improve simulation speed
2Speed
If behavioral code is executed on a simulation platform, then the code can be executed with full functionality, but the execution speed is slow compared to hardware execution
Solution Approach 1:
The testbench code is segmented into synthesizable and non-synthesizable portions. The synthesizable portion is executed on the hardware emulation platform for high-speed parallel execution, while the non-synthesizable behavioral code runs on the simulation platform, optimizing overall execution speed while maintaining productivity
Solution Approach 2:
An interface mechanism is introduced to mediate between the hardware emulation platform and the simulation platform. This intermediary enables efficient data exchange and coordination between the two execution environments, allowing the system to leverage both hardware speed and simulation functionality
3Productivity
If concurrent requests from hardware platform are processed sequentially in the simulator event queue, then the system remains simple to operate, but the productivity and throughput are significantly reduced
Solution Approach 1:
The event queue processing is segmented into multiple parallel processing streams. Instead of a single sequential processor handling all events, multiple threads or processes simultaneously process different portions of the event queue, thereby increasing throughput while maintaining operational simplicity through standardized processing interfaces
Solution Approach 2:
The event queue processing transitions from a single-dimensional sequential model to a multi-dimensional parallel model. Multiple processing threads operate concurrently on different event streams, adding the dimension of parallelism to improve throughput while managing complexity through structured event routing and synchronization mechanisms
Data Source
AI summary
The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.