Constraint-Based Testbench Simplification via Redundant Gate Merging
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Solution Overview
Problem
The computational cost of verifying complex system designs increases exponentially with the number of state and logic elements, necessitating an efficient method to identify and eliminate redundant logic elements to streamline the verification process.
Innovation Solution
The approach involves determining redundancies in a system model with constraints by selecting candidate redundant gates, replicating constraint cones, building merged models, and validating the candidate gates using speculatively reduced models to ensure equivalence and preserve constraint strength, thereby reducing the verification complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of state and logic elements in the system model increases, then the system can represent more complex designs, but the computational cost of verification increases exponentially
Solution Approach 1:
The patent merges redundant logic elements by identifying and combining equivalent state variables and logic gates. The merging process consolidates multiple redundant elements into a single representative element, reducing the overall system complexity while preserving verification accuracy. This directly addresses the contradiction by reducing the number of elements to verify without losing the ability to represent complex design behaviors.
Solution Approach 2:
The patent extracts and removes redundant logic elements from the system model through automated identification of equivalent state variables and gates. By extracting only the essential non-redundant elements needed for verification, the system reduces computational cost while maintaining the ability to represent complex design behaviors through the remaining essential elements.
2Productivity
If redundant logic elements are removed from the system model, then verification computational cost decreases, but the accuracy of constraint validation may be compromised
Solution Approach 1:
The patent performs preliminary analysis to identify and validate redundant logic elements before removing them from the system model. The equivalence checking and constraint validation are performed in advance on candidate elements for removal, ensuring that their elimination will not compromise verification accuracy. This preliminary validation step ensures reliability is maintained while enabling subsequent efficiency improvements.
Solution Approach 2:
The patent implements feedback mechanisms where the verification system continuously checks whether removed redundant elements actually affect constraint validation results. The equivalence checking process provides feedback on whether candidate redundant elements can be safely removed, and the system adjusts its reduction strategy based on this feedback to maintain validation accuracy while maximizing efficiency gains.
Data Source
AI summary
Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.