Testcase Checker System for Microprocessor Verification

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Solution Overview

Problem

Current methods for detecting invalid testcases in microprocessors, particularly those with boundedly undefined conditions, are inefficient and resource-intensive, as they rely on manual debugging and simple scanner scripts that fail to account for microarchitectural effects.

Innovation Solution

A testcase checker system that simulates execution on a microprocessor using an instruction set simulator and a checker module, processing logging data with rules to identify boundedly undefined conditions, allowing for efficient detection and classification of invalid testcases without requiring a pipeline model or RTL simulations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual debugging is used to detect invalid testcases, then detection accuracy can be maintained, but verification time and human effort increase significantly

Engineering Contradiction:

Improvetestcase detection accuracyVSAvoidverification time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent introduces an automated testcase checker as an intermediary system between testcase generation and verification. This checker uses instruction set simulation and rule-based analysis to automatically detect boundedly undefined conditions, replacing manual debugging while maintaining detection accuracy through systematic rule evaluation of logging data

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical manual debugging process with an automated computational system. The testcase checker uses instruction set simulators and automated rule processing to substitute human analysts, dramatically reducing verification time while maintaining detection capability through systematic analysis of execution logging data

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If simple scanner scripts are used to detect invalid testcases, then verification speed improves, but detection accuracy deteriorates due to inability to account for microarchitectural effects

Engineering Contradiction:

Improveverification speedVSAvoidtestcase detection accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary instruction set simulation and logging data collection before final testcase validation. By pre-processing testcases through instruction set simulation and capturing execution logs, the system prepares data in advance for rule-based analysis, enabling both speed and accuracy in the subsequent detection phase

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces instruction set simulation and logging mechanisms as intermediaries between simple scanning and final detection. These intermediaries capture microarchitectural execution details that simple scanners miss, providing enriched data to the rule-based detector without significantly impacting verification speed

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If comprehensive rule-based analysis is performed on all testcases, then detection accuracy improves, but resource consumption increases

Engineering Contradiction:

Improvetestcase classification accuracyVSAvoidcomputing resource consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies partial rule-based analysis by focusing rules specifically on detecting boundedly undefined conditions rather than performing comprehensive analysis on all testcase aspects. This selective application of rules maintains detection accuracy for the specific problem while reducing overall resource consumption by avoiding unnecessary analysis

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8972785B2Classifying processor testcases

Publication Date: 2015.03.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.