Tester IC With Dedicated Circuits And Programmable Logic
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Solution Overview
Problem
Current semiconductor testing systems face inefficiencies due to the presence of unused test circuits in ASICs and the general-purpose design of FPGAs, which can interfere with operations, require more resources, and make certain test circuits impracticable or impossible to implement.
Innovation Solution
A tester IC with dedicated test circuits coupled to programmable logic, allowing for specific configurations based on programming data to form a tester for semiconductor devices, isolating unused circuits and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASICs include multiple test circuits for different test applications, then test versatility is improved, but unused circuits interfere with intended operation and increase device complexity
Solution Approach 1:
The patent extracts and removes unused test circuits from the ASIC device before final assembly. The methodology involves identifying test circuits that will not be used for a specific test application and physically removing them from the ASIC, thereby eliminating interference from inactive circuits while maintaining the versatility of the device for different test applications.
Solution Approach 2:
The patent segments the test circuits into separate, identifiable components within the ASIC structure. Each test circuit is designed as a distinct module that can be independently activated or removed, allowing the system to maintain versatility while eliminating harmful interference from unused circuits through selective activation.
2Adaptability or versatility
If FPGAs use general-purpose programmable logic, then adaptability is improved, but implementation of certain test circuits becomes inefficient or impossible
Solution Approach 1:
The patent merges dedicated test circuits with programmable logic in a hybrid architecture. The dedicated circuits provide efficient, optimized test functionality for specific applications, while the programmable logic provides flexibility for configuration and adaptation. This combination achieves both implementation efficiency and adaptability.
Solution Approach 2:
The patent creates a multi-functional test system where dedicated test circuits can serve multiple purposes through programmable logic control. The same physical circuit infrastructure can be configured for different test applications by programming the logic elements, achieving universality without sacrificing implementation efficiency.
3Productivity
If test system controllers increase the number of channels for multi-site testing, then productivity is improved, but cost increases significantly
Solution Approach 1:
The patent segments the test system into modular components where individual test circuits and logic elements can be independently configured and activated. This segmentation allows the system to achieve multi-site testing capability by activating only the necessary number of channels for each specific test application, reducing overall system cost while maintaining high productivity when needed.
Data Source
AI summary
Methods and apparatus for providing a tester integrated circuit (IC) for testing a semiconductor device under test (DUT) are described. Examples of the invention can relate to an apparatus for testing a semiconductor device under test (DUT). In some examples, the apparatus can include an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits.