Testing Circuit Layout Area Reduction for Narrow Frame Displays
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Solution Overview
Problem
High pixel resolution display panels face challenges in accommodating an array of testing circuits due to limited space in the peripheral area, making it difficult to achieve a narrow frame effect.
Innovation Solution
The electronic device incorporates a testing circuit with a plurality of output channels that are electrically connected to some of the signal lines, and includes switches connected via these output channels. The number of output channels is less than the number of signal lines, allowing for reduced layout area and effective testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of output channels is reduced to less than the number of signal lines, then the layout area for the testing circuit is reduced, but the testing capability must be maintained through alternative configurations
Solution Approach 1:
The testing circuit is designed with multi-functionality where a reduced number of output channels can test multiple signal lines through various testing modes and configurations. The same output channels can be dynamically allocated to different signal lines for different testing operations, enabling one channel to serve multiple purposes and thereby reducing the total number of channels needed while maintaining comprehensive testing capability.
Solution Approach 2:
The testing circuit employs dynamic resource allocation where output channels can be dynamically assigned to different signal lines based on testing requirements. This dynamic configuration allows the same physical channels to test different signal lines at different times, effectively reducing the static hardware requirements while maintaining full testing coverage across all signal lines.
2Area of stationary object
If via holes are overlapped to share output channels, then the layout area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The design implements nested via hole structures where multiple via holes are vertically stacked and aligned to share common output channels. This nesting approach allows signal lines from different layers to converge to the same output channel through the stacked via holes, reducing the horizontal layout area while the via hole alignment and connection processes follow standard manufacturing procedures that manage complexity through established fabrication techniques.
Data Source
AI summary
An electronic device is provided. The electronic device includes a pixel array, a plurality of signal lines and a testing circuit. The signal lines are electrically connected to the pixel array. The testing circuit includes a plurality of output channels electrically connected to some of the plurality of signal lines and a plurality of switches. The plurality of switches are connected to the plurality of signal lines via the plurality of output channels. The plurality of output channels of the testing circuit are less than the plurality of signal lines in quantity. There are at least two via holes overlapping one of the plurality of output channels.