Testing Device Double-Frequency Signal Merging for High-Speed Memory
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Solution Overview
Problem
Conventional testing devices struggle to efficiently test high-frequency memory devices due to reduced testing efficiency and throughput, and potential errors arise from frequency multiplication methods.
Innovation Solution
A testing device and method that merges two testing signals to generate a double-frequency signal, allowing simultaneous testing of paired devices, thereby improving testing frequency and throughput by serial coupling of devices in socket groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency multiplication is used by changing circuit board interface to test high-frequency memory devices, then testing frequency can be increased, but testing efficiency and throughput are greatly reduced
Solution Approach 1:
The invention divides the testing system into multiple independent testing channels (first testing channel and second testing channel), each capable of operating at high frequency independently. This segmentation allows parallel testing of multiple devices simultaneously, thereby maintaining high throughput while achieving high testing frequency through frequency multiplication.
2Speed
If frequency multiplication is used to test high-frequency memory devices, then testing frequency can be increased, but testing accuracy is greatly reduced and potential errors are found
Solution Approach 1:
The invention introduces a signal distribution network as an intermediary that receives the high-frequency testing signal and distributes it to multiple testing channels. This intermediary approach ensures signal integrity is maintained during frequency multiplication by providing dedicated signal paths for each channel, thereby reducing errors and maintaining testing accuracy.
3Speed
If two I/O terminals of a tester are connected to one pin of the circuit board interface to achieve frequency multiplication, then high-frequency testing is enabled, but testing efficiency is greatly reduced
Solution Approach 1:
The invention merges multiple testing channels into a unified testing architecture where multiple devices are tested simultaneously using the same high-frequency signal source. By combining the testing functions of multiple channels and operating them in parallel, the system achieves both high-frequency capability and high testing efficiency.
Data Source
AI summary
A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.