Testing Land Diameter Design for Probe Contact Accuracy

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices shrink in size, the accuracy of electrical characteristic tests using testing lands on the lower surface of the wiring substrate is compromised due to reduced land diameter and pitch, leading to potential non-contact issues between probes and lands, which can result in inaccurate testing.

Innovation Solution

The implementation of a semiconductor device design where testing lands on the lower surface of the wiring substrate have a larger diameter than external lands, ensuring accurate electrical characteristic tests by maintaining contact with probes despite size reductions, and the use of specific contact pin structures to accommodate warping and machining variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the diameter of testing lands is reduced to shrink semiconductor device size, then the device size is reduced, but the contact accuracy between probes and testing lands deteriorates

Engineering Contradiction:
Improvesemiconductor device sizeVSAvoidcontact accuracy between probes and testing lands
Core Design Contradiction:
Volume of moving objectVSMeasurement precision

Solution Approach 1:

The patent applies local quality by differentiating the diameter of testing lands from external lands. Specifically, testing lands are designed with a larger diameter than external lands, creating a local distinction that ensures reliable probe contact while maintaining overall device miniaturization. This localized enhancement at critical testing points resolves the contradiction between small size and testing accuracy.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the pitch between testing lands is reduced to increase terminal density, then the terminal density is increased, but the probe contact reliability deteriorates

Engineering Contradiction:
Improveterminal densityVSAvoidprobe contact reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements local quality by applying the larger diameter design specifically to testing lands while maintaining smaller external lands for high density. This selective approach allows the testing lands to provide reliable probe contact even when pitch is reduced, while external lands maintain high density for signal terminals.

Inventive Principle:
Principle #3Local quality

3Reliability

If the diameter of testing lands is increased to ensure probe contact, then the contact reliability is improved, but the device size increases

Engineering Contradiction:
Improveprobe contact reliabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent resolves this contradiction by applying the larger diameter only to testing lands where probe contact is critical, while keeping external lands smaller. This localized enhancement provides the necessary contact reliability without proportionally increasing the overall device size, as the larger diameter is confined to specific testing points rather than applied universally.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses partial action by enhancing only the critical testing lands with larger diameter, rather than increasing the size of all lands. This selective enhancement provides sufficient probe contact reliability without the excessive size increase that would result from uniformly enlarging all landing areas.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8404497B2Semiconductor device and method of manufacturing the same
Publication Date: 2013.03.26 RENESAS ELECTRONICS CORP
  • US8404497B2 patent drawing
  • US8404497B2 patent drawing
  • US8404497B2 patent drawing

AI summary

A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.